
Citation 
 Permanent Link:
 http://ufdc.ufl.edu/UF00097373/00001
Material Information
 Title:
 Physicsbased thermal impedance models for the simulation of selfheating in semiconductor devices and circuits
 Creator:
 Brodsky, Jonathan Scott, 1969 ( Dissertant )
Fox, Robert M. ( Thesis advisor )
Law, Mark E. ( Reviewer )
Fossum, Jerry G. ( Reviewer )
Eisenstadt, William R. ( Reviewer )
Harris, John G. ( Reviewer )
Hsu, ChenChi ( Reviewer )
 Place of Publication:
 Gainesville, Fla.
 Publisher:
 University of Florida
 Publication Date:
 1997
 Copyright Date:
 1997
 Language:
 English
 Physical Description:
 ix, 257 leaves : ill. ; 29 cm.
Subjects
 Subjects / Keywords:
 Electric current ( jstor )
Electric potential ( jstor ) Equivalent circuits ( jstor ) Modeling ( jstor ) Oxides ( jstor ) Silicon ( jstor ) Simulations ( jstor ) Thermal resistance ( jstor ) Three dimensional modeling ( jstor ) Transistors ( jstor ) Dissertations, Academic  Electrical and Computer Engineering  UF ( lcsh ) Electrical and Computer Engineering thesis, Ph. D ( lcsh ) Semiconductors  Heat treatment ( lcsh ) Semiconductors  Thermal properties ( lcsh )
 Genre:
 bibliography ( marcgt )
theses ( marcgt ) federal government publication ( marcgt ) nonfiction ( marcgt )
Notes
 Abstract:
 Inherent in the operation of semiconductor devices is selfheating, an
increase in operating temperature due to a device's own power dissipation. The
magnitude of the selfheating effect can be quantified by the value of the thermal
impedance, which describes the dynamic response of the device temperature to
variations in device power. The thermal impedance is determined primarily by
material properties and device structure. The implication of the selfheating effect is
that the change in temperature can alter the operating characteristics of a device,
which in turn, can affect circuit performance.
The primary focus of this dissertation is the development of physicsbased
models for the thermal impedances of semiconductor devices. Models for the thermal
impedances of bipolar and fieldeffect transistors, on both bulk and silicononinsulator (SOI) substrates, are presented. All of the thermal impedance models were
derived from the timedependent heat conduction equation, resulting in compact
analytic expressions for the thermal impedances. The physical nature of the thermal
impedance models allows them to scale with the device structure and material
properties, and they successfully reproduce results from both measurements and
threedimensional finiteelement simulations. A circuit model for thermal coupling
between transistors in a common substrate is also presented. The coupling model was
used in conjunction with the bulk bipolar thermal impedance model to extract a
lumped electrothermal model for multipleemitter bipolar transistors. The secondary objective of this work is the provision of an approach for
incorporating these models into circuit simulators. It has been shown that the thermal
impedance models can be represented by thermal equivalent circuits made up of
resistors and capacitors, making them suitable for efficient circuit simulation. The
computer program TIPP (Thermal Impedance PreProcessor) is introduced. TIPP
was developed to provide circuit simulators with convenient algorithms for
generating thermal equivalent circuits. TIPP can calculate the component values for
thermal equivalent circuits from either physical models or measured data, and is
easily modified to interface with different circuit simulators.
 Thesis:
 Thesis (Ph. D.)University of Florida, 1997.
 Bibliography:
 Includes bibliographical references (leaves 247256).
 Additional Physical Form:
 Also available on World Wide Web
 General Note:
 Typescript.
 General Note:
 Vita.
 Statement of Responsibility:
 by Jonathan Scott Brodsky.
Record Information
 Source Institution:
 University of Florida
 Holding Location:
 University of Florida
 Rights Management:
 This item is a work of the U.S. federal government and not protected by copyright pursuant to 17 U.S.C. Â§105.
 Resource Identifier:
 028004815 ( AlephBibNum )
37823695 ( OCLC ) ALP2249 ( NOTIS ) 22109162 ( ALEPH )

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PHYSICSBASED THERMAL IMPEDANCE MODELS FOR THE SIMULATION OF
SELFHEATING IN SEMICONDUCTOR DEVICES AND CIRCUITS
By
JONATHAN SCOTT BRODSKY
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
1997
This work is dedicated to my parents,
Lawrence and Jeraldine,
my brother Matthew and sister Alexandra.
ACKNOWLEDGEMENTS
First, I wish to express my deepest gratitude to my advisor Dr. Robert M.
Fox. His constant support and patient guidance provided a clear path for my research.
It is both a pleasure and a privilege to have worked with Dr. Fox. I thank Drs. Mark
E. Law and Jerry G. Fossum for extending their expertise and help to my unending
questions. I would also like to thank Drs. William R. Eisenstadt, John G. Harris and
ChenChi Hsu for their willingness to serve on my supervisory committee. I am also
very grateful to Mary Turner for all of her help throughout my graduate career.
I would like to acknowledge and thank the Semiconductor Research
Corporation (SRC) for the financial support that made this research possible. I am
also grateful to Dr. Surya Veeraraghavan for his guidance and friendship during my
internship at Motorola.
I would like to thank the "TCAD elders", and now my friends, Keith
Green, Dongwook Suh, PingChin Yeh, Haeseok Cho, ChihChuan Lin, MingChang
Liang and Scott Miller, for helping me get comfortable in my new surroundings and
setting the standard of excellence.
I am also grateful to my good friends/workmates/"happy hour buddies"
Srinath Krishnan, Samir Chaudhry, David Zweidinger, Omer Dokumaci, MingYeh
Chuang, Dukhyun Chang, Susan Earles, Hernan Rueda, Glenn Workman and Meng
Hsueh Chiang, for all of the enlightening discussions, the Friday lunch tradition and
the weekend adventures.
There is a very special group of individuals who have my admiration and
love for the friendships they have given me. I would like to thank my best friends
Douglas Weiser, Martin Weiss, Stephen Cea, Edward Cometz and Peter Lynch.
I can not completely express the role my family has played in my life and
in the completion of this dissertation. For simple words seem to diminish their
unconditional and unending love and support. I owe everything I have, everything I
have done and everything I am, to my family. I give my deepest love to my parents,
Jeraldine and Lawrence Brodsky, my brother Matthew and my sister Alexandra.
Finally, I am grateful to all of the wonderful friends that I met in
Gainesville for making this period of my life truly enjoyable.
TABLE OF CONTENTS
ACKNOWLEDGEMENTS .................................
. . . . . . . iii
ABSTRACT ........................................................ viii
1 INTRODUCTION ................................................ 1
1.1 SelfHeating Effects in Semiconductor Devices
1.1.1 Bipolar Transistors ..................
1.1.2 FieldEffect Transistors ..............
1.2 SelfHeating Effects in Semiconductor Circuits
1.2.1 SmallSignal Circuit Performance ......
1.2.2 LargeSignal Circuit Performance ......
1.3 SelfHeating Effects in Parameter Extraction ..
1.4 The Simulation of SelfHeating Effects .......
1.5 Thermal Equivalent Circuits. ...............
. . . . . . . . . . . .
......................3
......................6
. . . . . . . . . . . 8
. . . . . . . . . . . 8
..................... 11
. . . . . . . . . . . 12
. . . . . . . . . . . 13
1.6 The Need for PhysicsBased Thermal Impedance Models ..
1.7 O organization ............... ......................
. . . . . . 16
........ .. 20
........... 25
2 A THREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR
JUNCTIONISOLATED BIPOLAR TRANSISTORS. .................... 27
2.1 Introduction .......................................
..........27
2.2 Derivation of the SingleEmitter BJT/HBT Thermal Impedance Model... 28
2.2.1 Modification for Finite Wafer Thickness ................... .. 39
2.2.2 Effects of Interconnect Metallization on the Thermal Impedance ... 43
2.2.3 A Model for the Thermal Impedance of the Emitter Interconnect... 49
2.2.4 Effects of Isolation Structures on the Thermal Impedance ......... 52
2.3 Verification of the SingleEmitter Thermal Impedance Model .......... 61
2.4 Derivation of the MultipleEmitter BJT/HBT Thermal Impedance Model. 66
2.5 Verification of the MultipleEmitter Thermal Impedance Model ........ 72
2.6 Summary................... ............................... 76
3 A CIRCUIT MODEL FOR THERMAL COUPLING AND A LUMPED
ELECTROTHERMAL MODEL FOR BULK MULTIPLEEMITTER BIPOLAR
TRANSISTORS ............... .............................. 77
3.1 Introduction ................................................77
3.2 A Circuit Model for Thermal Coupling ............................ 80
3.3 A Lumped Electrothermal Model for MultipleEmitter BJT/HBT's ...... 86
3.3.1 A Review of BaseCurrent Thermometry. ................... .. 90
3.3.2 Generation of the Lumped Electrothermal Model ............... 91
3.4 Verification of the Lumped Electrothermal Model ................... 96
3.5 Summary ............ ....... ....... ........................ 101
4 A THREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR
VERTICAL BIPOLAR TRANSISTORS FABRICATED WITH FULL
DIELECTRIC ISOLATION ....................................... 103
4.1 Introduction ........................ ........... ....... .. 103
4.2 Derivation of the DIBJT Thermal Impedance Model ................ 106
4.2.1 Derivation of the BuriedOxide HeatTransfer Coefficient ....... 116
4.2.2 Derivation of the Trench HeatTransfer Coefficient ........... 120
4.2.3 Effects of Interconnect Metallization on the Thermal Impedance . 126
4.2.4 A Model for the Thermal Impedance of the Emitter Interconnect. 129
4.3 Verification of the DIBJT Thermal Impedance Model ............... 132
4.4 Derivation of a Compact DIBJT Thermal Resistance Model .......... 134
4.5 Verification of the DIBJT Thermal Resistance Model ............... 146
4.6 Summary................................................... 149
5 A THREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR BULK
METALOXIDESEMICONDUCTOR FIELDEFFECT TRANSISTORS .. 150
5.1 Introduction ........................... ..................... 150
5.2 Derivation of the Bulk MOSFET Thermal Impedance Model .......... 153
5.2.1 The Linear Source Thermal Impedance ................... .. 161
5.2.2 The Saturated Source Thermal Impedance ................. .. 164
5.2.3 Effects of the Device Interconnects on the Thermal Impedance ... 165
5.2.4 Effects of Isolation Structures on the Thermal Impedance ........ 171
5.3 Verification of the Bulk MOSFET Thermal Impedance Model ........ 176
5.4 Summary.................. ............................... 182
6 A QUASITHREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR
SILICONONINSULATOR METALOXIDESEMICONDUCTOR FIELD
EFFECT TRANSISTORS ........................................ 184
6.1 Introduction ................... ........................... 184
6.2 Derivation of the SOI MOSFET Thermal Resistance Model .......... 187
6.3 Verification of the SOI MOSFET Thermal Resistance Model ......... 202
6.4 Derivation of the SOI MOSFET Thermal Impedance Model .......... 204
6.5 Verification of the SOI MOSFET Thermal Impedance Model ......... 212
6.6 Summary................................................ 216
7 THE THERMAL IMPEDANCE PREPROCESSOR: TIPP .............. 219
7.1 Introduction ............................................... 219
7.2 A Description of TIPP ........................................ 220
7.3 Generation of Thermal Equivalent Circuits ........................ 225
7.3.1 Approximation of the Thermal Equivalent Poles/Time Constants. 226
7.3.2 Calculation of the Thermal Equivalent Components ............ 230
7.4 The Interface Between TIPP and Circuit Simulators ................. 232
7.5 Summary................................................... 234
8 CONCLUSIONS AND RECOMMENDATIONS FOR FUTURE WORK... 238
8.1 Conclusions ............................................... 238
8.2 Recommendations for Future Work. .......................... 240
8.2.1 The Temperature Dependence of the Thermal Conductivity ...... 240
8.2.2 Models for Thermal Effects Due to Advanced Isolation ......... 242
8.2.3 A Model for Thermal Coupling in SOI MOSFET Circuits ....... 243
REFERENCES ....................................................... 247
BIOGRAPHICAL SKETCH .......................................... . 257
Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy
PHYSICSBASED THERMAL IMPEDANCE MODELS FOR THE SIMULATION OF
SELFHEATING IN SEMICONDUCTOR DEVICES AND CIRCUITS
By
Jonathan Scott Brodsky
August 1997
Chairman: Robert M. Fox
Major Department: Electrical and Computer Engineering
Inherent in the operation of semiconductor devices is selfheating, an
increase in operating temperature due to a device's own power dissipation. The
magnitude of the selfheating effect can be quantified by the value of the thermal
impedance, which describes the dynamic response of the device temperature to
variations in device power. The thermal impedance is determined primarily by
material properties and device structure. The implication of the selfheating effect is
that the change in temperature can alter the operating characteristics of a device,
which in turn, can affect circuit performance.
The primary focus of this dissertation is the development of physicsbased
models for the thermal impedances of semiconductor devices. Models for the thermal
impedances of bipolar and fieldeffect transistors, on both bulk and siliconon
insulator (SOI) substrates, are presented. All of the thermal impedance models were
derived from the timedependent heat conduction equation, resulting in compact
analytic expressions for the thermal impedances. The physical nature of the thermal
impedance models allows them to scale with the device structure and material
properties, and they successfully reproduce results from both measurements and
threedimensional finiteelement simulations. A circuit model for thermal coupling
between transistors in a common substrate is also presented. The coupling model was
used in conjunction with the bulk bipolar thermal impedance model to extract a
lumped electrothermal model for multipleemitter bipolar transistors.
The secondary objective of this work is the provision of an approach for
incorporating these models into circuit simulators. It has been shown that the thermal
impedance models can be represented by thermal equivalent circuits made up of
resistors and capacitors, making them suitable for efficient circuit simulation. The
computer program TIPP (Thermal Impedance PreProcessor) is introduced. TIPP
was developed to provide circuit simulators with convenient algorithms for
generating thermal equivalent circuits. TIPP can calculate the component values for
thermal equivalent circuits from either physical models or measured data, and is
easily modified to interface with different circuit simulators.
CHAPTER I
INTRODUCTION
1.1 SelfHeating Effects in Semiconductor Devices
The physical properties of the materials used to fabricate semiconductor
transistors depend on temperature. Therefore, the operating characteristics of a
transistor (e.g. electrical currents and potentials), which are determined by the
material properties, are also temperature dependent. The temperature at which a
transistor operates is determined by the temperature of the surrounding environment
(referred to as the "local ambient temperature") and the power dissipated in the
device (referred to as the "selfheating effect"). Therefore, the timedependent
temperature of a transistor can be expressed as
t
T(t) = Tamb + P(t')hTH(tt')dt', (1.1)
0
where hTH is the thermal impulse response and P is the instantaneous power. The
second term on the righthand side of (1.1) represents the temperature rise in the
device
AT(t) = P hTH, (1.2)
where 0 is the convolution operator. The temperature rise can also be expressed in
the frequency domain as
AT(t) =  [ZTH(S) P(s)], (1.3)
where 1 represents the inverse Laplace transform and ZTH(s) is the thermal
impedance. The thermal impedance of a transistor describes the dynamic response of
the device temperature to variations in device power, and is determined primarily by
the material properties and the structure of the device. The transient thermal
impedance can be defined as
ZTH(t) = 1 ZTH(s), (1.4)
which represents the normalized thermal step response.
Since the power dissipation in (1.1) is determined by the operating
characteristics of a transistor, it depends on temperature such that
P = P(T) = Idev(T) Vdev(T), (1.5)
where Idev(T) and Vdev(T) represent general currents and potentials within a given
device, respectively. Consequently, there is feedback between the thermal and
electrical operation of the device. Whereas the transistor temperature is usually
assumed to be constant, the electrothermal coupling implied by (1.1) and (1.5) shows
that the temperature actually varies with the device operation. Thus, to fully
characterize the operation of semiconductor transistors, both the electrical and
thermal behavior should be determined.
1.1.1 Bipolar Transistors
In the forwardactive mode, the operating characteristics of bipolar
junction and heterojunction transistors (BJT's and HBT's) are controlled by the
injection and diffusion of minority carriers in the base region. For an npn transistor,
electrons are injected across the forwardbiased base/emitter junction, causing an
exponential increase in the minority carriers in the base. The electrons diffuse across
the base and are swept into the collector by the reversedbiased base/collector
junction. For a fixed base/emitter voltage, assuming negligible recombination in the
quasineutral base, the collector current can be expressed as
2 qVBE'
Ic(T) ni (T) exp EkT (1.6)
where ni is the intrinsic carrier concentration, q is the electron charge, k is
Boltzman's constant and T is temperature. The overall temperature dependence of
(1.6) is dominated by the relation between the intrinsic carrier concentration and
temperature, given by
2 "Eg
n (T) = N. N, exp.. ) (1.7)
where Eg is the semiconductor bandgap energy and Nc and Nv are the effective
density of states in the conduction and valence bands, respectively. The junction
voltage is always less than the bandgap and therefore, an increase in temperature
causes an exponential increase of minority carriers in the base, resulting in an
increase in collector current. Since the collector current is a significant component
of the power dissipation in a BJT, selfheating results in a regenerative feedback
between the collector current and the temperature of the device. This positive
feedback can lead to the destructive phenomenon of thermal runaway in BJT's
[Shu90].
For fixed base current, the collector current can be expressed as
Ic(T) = P(T) IB, (1.8)
where P(T) is the commonemitter current gain. For moderate injection levels, the
current gain can be approximated by the ratio of the electrons injected into the base
to the holes backinjected from the base to the emitter. This ratio, and hence p(T),
are typically high since the emitter usually has a higher doping level than the base.
Due to heavydoping effects in the emitter, the emitter bandgap is typically less than
that in the base so that
P(Y) NDE AEgN
(T) NB expAE ), (1.9)
NAB V k!T
where AEg is the bandgap difference between the emitter and base, and NDE and
NAB are the doping concentrations in the emitter and base, respectively. As shown
by (1.9), the current gain is greater at higher temperatures; consequently, the
collector current is, again, an increasing function of temperature. The rate of increase
with temperature in this case, however, is not as significant as that for a device biased
with a fixed base voltage. Therefore, the selfheating effect is not as substantial in
BJT's driven by a fixed base current.
HBT's are bipolar devices that use bandgap engineering in either the
emitter or base region to improve the current gain over homojunction BJT's. The
resulting bandgap in the emitter is wider than that in the base, so that the potential
barrier induced by the bandgap discontinuity effectively impedes the injection of
carriers from the base to the emitter. When biased with a fixed base voltage, the
temperature dependence of an HBT is similar to that of a standard BJT. However,
when an HBT is driven with a fixed base current, the temperature dependence of the
collector current is quite different than that of a BJT. While the collector current in
this case can still be determined from (1.8), the commonemitter current gain is now
expressed as
NDE (AEg'
P1(T) exp (1.10)
NAB kT
As a result of the bandgap being wider in the emitter than in the base, the sign of the
exponential argument is now positive. Therefore, as opposed to a standard BJT, the
current gain and the collector current decrease with increasing temperature. As a
result, selfheating in HBT's can lead to the noncatastrophic failure mechanism
known as current collapse [Sei93].
To reduce the effects of parasitic resistances and currentcrowding, large
bipolar devices are commonly fabricated using multiple devices connected in parallel
[Shu90]. Multipleemitter devices, both BJT's and HBT's, are capable of operating
at high frequencies under high power densities [Win67, Mar93, Liu95b]. However,
multipleemitter devices suffer from more complex selfheating effects due to the
thermal interactions among neighboring devices. The thermal coupling leads to
lateral temperature gradients across the device, resulting in the inner emitters
operating at higher temperatures. Due to the positive feedback between junction
temperature and junction current, the inner devices carry more current than those at
the outer extremes. As the current density in the inner emitters increases, the self
heating effect in these devices accelerates. The premature activation of thermal
runaway in BJT's and current collapse in HBT's is attributed to this thermal
instability inherent in multipleemitter devices [Win67, Liu93, Kag94, Lio94,
Lio96].
1.1.2 FieldEffect Transistors
For MetalOxideSemiconductor FieldEffect Transistors (MOSFET's)
operating in strong inversion, the current characteristics are determined by the drift
current of carriers in the inverted channel region. For small drain voltages, a
MOSFET operates in the linear region where the carrier velocity depends on the
longitudinal electric field in the channel. In the linear region, the drain current can
be approximated as
ID(T) oc (T). VGs Vt(T) DS, (.1)
where 1p(T) is the carrier mobility, Vt(T) is the threshold voltage, and VGS and VDS
are the applied voltages between the gate and source and drain and source,
respectively. At higher drain voltages, the electric field at the drain end of the
channel is large enough to cause the carrier velocity to saturate. In the saturation
region, the drain current can be expressed as
ID(T) Qc(VGs, VDS, st(T)) vsat(T), (1.12)
where Qc is the channel charge and vsat(T) is the saturated carrier velocity.
The overall temperature dependence of (1.11) and (1.12) are dominated
by the sensitivity of the carrier mobility to changes in temperature. Due to increased
lattice scattering at higher temperatures, mobility decreases as temperature increases.
The reduction in mobility leads to a decrease in drain current, which implies that the
drain current of a MOSFET is a decreasing function of temperature. At high power
dissipation levels, the selfheating effect can cause the drain current to drop below
the ambient temperature value. In such cases, the output conductance becomes
negative, and the device exhibits a negative dynamic resistance (NDR) [Sha83].
MOSFET's fabricated on silicononinsulator (SOI) substrates have
temperature dependence that are similar to those of their bulk counterparts, though
the effects of selfheating can be enhanced due to the low thermal conductivity of the
insulating layers. For nonfully depleted (NFD) SOI MOSFET's, however, floating
body effects further complicate the thermal effects [Wor97]. Impactionization
induced floatingbody effects are known to cause the kink, or increase in drain
current, in NFD SOI MOSFET's. The kink is affected by selfheating in two ways.
First, at elevated temperatures, the onset of the impactionization is retarded.
Second, an increase in recombination in the quasineutral body reduces the
thresholdvoltage shift caused by the impactionization. Therefore, in addition to a
reduction in drain current due to mobility effects, selfheating also reduces the
current in NFD SOI MOSFET's through temperaturedependent floatingbody
effects.
1.2 SelfHeating Effects in Semiconductor Circuits
Since the operating characteristics of transistors are affected by
temperature, the integrated circuits that depend on these transistors will also be
affected by changes in temperature. In modern digital circuits, the high switching
speeds of the transistors, the relatively slow time constants associated with the
temperature response and the low static power dissipation, all help reduce the
instantaneous temperature rise. Consequently, selfheating effects are typically
negligible in digital circuits. On the other hand, analog circuit applications
commonly have significant power dissipation and can operate at frequencies which
are comparable to the thermal timeconstants. Therefore, analog circuits are
generally more prone to selfheating effects.
1.2.1 SmallSignal Circuit Performance
The effect of selfheating on smallsignal BJT characteristics was derived
by Mueller and investigated in bipolar circuits by Fox et al. [Mue64, Fox93b]. The
twoport smallsignal admittance parameters, in the presence of selfheating, were
shown to be
YmnE + DmZTHImIn (1.13)
mn 1 DmZTHP
where ymnE are the admittance parameters neglecting selfheating, and Dm
represents the variation of the current Im with temperature. The denominator of
(1.13) establishes the sensitivity of the admittance parameters to power, and has a
significant impact as DmZTHP approaches unity. The effect of the denominator
generally becomes important only at high power dissipation. However, as the thermal
impedance increases (i.e. due to device scaling), the power level that defines the
threshold for selfheating effects will decrease. The second term in the numerator of
(1.13) shows that the effect of selfheating on the admittance parameters is also
proportional to the operating currents. For yll and y21 the selfheating term in the
numerator is small so that yll =YlE and y21 =Y21E. However, the effect of self
heating can be substantial in the numerators of yl2 and y22, even at moderate current
levels. The thermal effects on these parameters can result in a coupling between the
collector output admittance and the impedance of the basedriving source. Also, as
shown in Figure 1.1, there can be a significant reduction in the voltage gain of BJT
amplifiers.
The smallsignal performance of analog MOSFET circuits can also be
affected by selfheating. For moderate power levels, the thermal effects are similar
to those in bipolar circuits. However, as mentioned previously, the drain current of a
MOSFET decreases with increasing temperature, and significant selfheating can
induce NDR. The effect of a negative output conductance can be investigated by
examining the voltage gain of a MOSFET amplifier. As shown by Fox and Brodsky
[Fox93a], if the devices in the amplifier enter a region of negative output
conductance, the gain of the amplifier changes polarity. For an inverting amplifier,
102 104 106 108
Frequency, (Hz)
1010
The effect of selfheating on the smallsignal gain of a BJT differential
amplifier. The data was simulated using a version of SPICE, which was
modified to account for dynamic variations in temperature [Zwe97],
and the thermal impedance model for bipolar transistors presented in
Chapter Two.
300
200
100
0
Figure 1.1
selfheating effects can therefore cause the gain to become noninverting, resulting
in hysteresis in the amplifier's output characteristics.
1.2.2 LargeSignal Circuit Performance
The effects of selfheating on the largesignal operation of analog bipolar
circuits was investigated by Fox et al. [Fox93b]. The types of circuits that are
sensitive to thermal effects are typically those that depend on the precise control of
BJT characteristics. For example, the mismatch in the reference and output currents
of a current mirror can be increased due to selfheatinginduced differences in the
operating conditions of the transistors. Translinear circuits and bandgap voltage
references can also be affected by selfheating due to their strong dependence on the
thermal voltage. Thus, neglecting selfheating can result in significant discrepancies
between the ideal and actual operation of these types of circuits. The largesignal
transient operation of analog circuits is also affected by selfheating. The long time
constants of the thermal characteristics can effectively slow down the electrical
response of a circuit. Fox et al. showed that the fivepercent settling time of a Gilbert
multiplier increased by over an order of magnitude due to selfheating [Fox93b].
While the errors caused by selfheating can be reduced by careful circuit design, they
can not be completely eliminated.
1.3 SelfHeating Effects in Parameter Extraction
The extractions necessary to determine the behavioral characteristics of a
semiconductor transistor are often performed at bias levels that cause moderate to
highpower dissipation. Typically, the parameters that are extracted are assumed to
correspond to the ambient temperature at which the measurements are carried out.
However, at significant power levels, selfheating will cause a temperature rise in the
device. Neglecting the temperature rise that can occur during the measurements can
lead to erroneous results [Zwe97]. For example, the Early voltage, VA, of a BJT is
commonly extracted from the slope of the IC VCE characteristics in the linear region
of operation. If selfheating is significant, the slope of the output curves depends on
the source that is driving the base [Fox93b]. Therefore, the exact meaning of the
value extracted for VA would be ambiguous unless the thermal effects were taken
into account.
Various methods have been proposed for removing the effects of self
heating from parameter extraction. One approach augments a standard extraction
routine with measurements designed to determine the thermal characteristics of the
device. The full set of parameters can then be input to a global optimization routine
to generate electricalonly parameters that are independent of selfheating [Zwe97].
Other techniques attempt to directly remove the effects of selfheating from the
parameter extraction measurements by making the temperature rise in the given
device negligible. The temperature rise can be minimized by performing the
extractions in lowpower regions, or by using complex highspeed measurements
[Tu94, Jen95]. Since the device is not allowed to heat, the resulting device parameter
set would be approximately devoid of selfheating effects, and would essentially
correspond to the given device operating under isothermal conditions. Consequently,
the resulting electrical parameters would only pertain to device operation for low
power or highspeed circuit applications, and would not convey the proper device
characteristics for applications that experience substantial selfheating effects. Thus,
for a set of electricalonly parameters to correctly represent the characteristics of a
device, over a wide range of operating conditions and biases, it should be augmented
by additional parameters that describe the thermal attributes of the device.
1.4 The Simulation of SelfHeating Effects
As shown in the previous sections, the operating characteristics of both
individual transistors and circuits depend on temperature. Due to selfheating, the
effective operating temperature depends on power dissipation and can therefore vary
under different operating conditions.
By solving the timedependent heat conduction equation and energy
balance equations for electrons and holes, numerical device simulators can model
phenomena associated with dynamic selfheating in individual transistors [Lia94].
While this approach is invaluable for examining the detailed physics that govern the
operation of semiconductor devices, it is impractical for simulating all but the
simplest of circuits. Therefore, to investigate the effects of dynamic selfheating on
a broad range of circuits, a more efficient simulation approach is necessary.
The standard version of most circuit simulators such as Berkeley SPICE
[Nag75] and HSPICE [Hsp92], treat temperature as a static global parameter. This
has two significant implications. All of the semiconductor devices in a simulation
operate at the same temperature, and that temperature remains constant throughout
the simulation. Due to these constraints, a circuit simulator may not accurately
represent the physical operation of a circuit, where spatial and temporal variations of
the temperature can cause each device to operate at its own local temperature. To
account for the temperature dependence of a circuit's operation, circuit simulators
should be capable of independently tracking the dynamic temperature of each device
in the circuit.
A common approach for creating an electrothermal circuit simulator
(ETCS) uses the concept of the thermal impedance and the analogy between
electrodynamics and heat flow to account for dynamic temperature variations. This
approach allows temperature to be represented as an electrical potential and power
as an electrical current [Lee96, Zwe97]; therefore, the local operating temperature of
a device can be thought of as simply another "bias" condition. To facilitate the
temperature "bias" condition, an external node is added to a given compact device
model [McA92, Fos95, Lee96, Zwe97]; such a configuration is shown in Figure 1.2.
Attached to this node, internal to the device model, is a controlled current source that
represents the instantaneous power dissipation. The parameter set for the device
model should be modified to include the correct temperature dependence. When the
modified device model is used for a circuit simulation, a thermal impedance (and, in
some case, a voltage source to represent the reference ambient temperature) can be
T0p(t)
p(t)
I
Tamb
A generalized schematic showing a common method for modifying a
compact device model to include temperature as a variable. The dashed
box outlines the new model with the added temperature node; DEVICE
represents the original electricalonly model.
IL
I
Figure 1.2
____
attached to the new external node. Therefore, the voltage generated at this additional
node represents the local temperature of the device. The electricalonly device model
is first solved at the ambient temperature; this solution results in an initial guess for
the device power dissipation. This power is then used to calculate the temperature
rise in the device. Once the approximate local operating temperature is calculated, it
is used to update the temperaturedependent model parameters, which are used to
recalculate the electrical bias potentials and currents of the device model. This
procedure is repeated until selfconsistent solutions for the temperature and electrical
biases are reached. Thus, an effective operating temperature can be independently
calculated for each device in a simulation, and that temperature can now vary with
the operating point.
1.5 Thermal Equivalent Circuits
The data that quantify the thermal impedance of a transistor are typically
in the form of discrete data points for the temperature rise, normalized to a unitstep
increase in power dissipation, versus time or frequency. In such a format, the thermal
impedance data are not readily accessible by an ETCS. While data in a tabular format
can be used without much complexity for DC and AC simulations, an inefficient
convolution computation would be required to use the data for transient simulations.
Therefore, a representation for the thermal impedance is needed that both accurately
models the physical data and can be easily incorporated into an ETCS for efficient
DC, AC and transient simulations.
In an ETCS, when a current representing the power dissipation in a
transistor is applied to the thermal impedance, ZTH, the resulting voltage represents
the temperature rise in that transistor. By invoking the analogy between
electrodynamics and heat flow, the thermal impedance can be represented as an
electrical impedance. Common representations for the electrical impedance circuits
are shown in Figure 1.3. The resistances and capacitances that comprise the
impedance effectively represent the lumped threedimensional thermal resistance
and heat capacity of the semiconductor device structure. Therefore, the overall
electrical network can be referred to as a thermal equivalent circuit. The values for
the individual elements of a thermal equivalent circuit can easily be determined by
numerically fitting the circuit to existing thermal impedance data. Thermal
equivalent circuits are directly applicable for DC and AC electrothermal simulations
since, in such cases, the voltage drop across the network is simply equal to the
product of the current and the network resistance or impedance. In addition, such
networks inherently provide an efficient method for effecting the necessary transient
convolution.
As will be shown in the subsequent chapters of this dissertation, the
fundamental nature of heat flow is that of a distributed system. The dynamic
temperature rise in a device due to selfheating can occur over three or more decades
of time or frequency. A single time constant associated with a simple exponential
function can not represent the distributed behavior of selfheating. Consequently, the
network response of the singlepole thermal equivalent circuits which have been
proposed in previous works [McA92, Bau93, Lee93, Tu94], will not accurately
rth2
Cthl Cth2 Cth3
I I
(a)
rthl rth2 rth3
" I ......
I I IAA
Cthl
Cth2
Cth3
Thermal equivalent circuits used to represent a thermal impedance for
circuit simulation: a) Cauer network representation; b) Foster network
representation.
Figure 1.3
rthl
rth3
model the dynamic thermal impedance. Thermal equivalent circuits consisting of
cascaded resistor/capacitor stages, as exemplified in Figure 1.3, effectively provide
a distributed network response, and therefore allow a more accurate representation
of a dynamic thermal impedance [Bro93].
In the work by Szekely and Van Bien [Sze88], the Foster circuit
(Figure 1.3b) was shown to be an invalid representation of a discretized thermal
network. This point is valid in the context of numerical simulations (e.g. finite
difference or finite element) where the transistor structure is modeled by a
distributed thermal network. In that case, the nodetonode capacitances of the Foster
network do not have physical meaning and the Cauer network would be the proper
physical discretization of the given thermal domain. However, in this dissertation,
the thermal equivalent circuit is simply a numerical representation of a thermal
impedance, and the validity of its format is moot. Yet, for the purpose of representing
a lumped thermal impedance in an ETCS, the Foster network form offers an
important advantage over the Cauer form: the time constants associated with a given
Foster network are independent of any surrounding circuit elements. This
characteristic is beneficial when individual thermal equivalent circuits must be
connected to model different components of a transistor structure or the thermal
interactions between transistors. Therefore, the Foster network form will be assumed
for any thermal equivalent circuits within this dissertation.
1.6 The Need for PhysicsBased Thermal Impedance Models
In the previous two sections, the concept of the thermal impedance is
adopted to model the temperature rise in a transistor as a function of that device's
power dissipation. For the purpose of circuit simulation, the thermal impedance can
be represented by a network of resistances and capacitances that effectively represent
the lumped thermal characteristics of a transistor. To successfully synthesize a
thermal equivalent circuit, tangible data for the thermal impedance are necessary.
One approach to obtain the thermal impedance of a transistor is to extract
it from measurements [Lee95, Zwe96]. While this empirical approach provides
accurate temperature information, such measurements are somewhat difficult, for
several reasons. To begin with, thermal measurements are very timeconsuming. The
extraction procedure is generally divided into two steps, the first of which dominates
the total measurement time. This step is required to calibrate the relation between the
temperature and the physical characteristic that is being used to monitor the
temperature (e.g. the base current and drain current in bipolar and fieldeffect
transistors, respectively). The calibration is performed at multiple ambient
temperatures at DC and is thus limited by the long time constants associated with
steadystate heat flow. To make such thermal measurements requires special
measurement equipment such as a thermal wafer chuck or oven to accurately control
the temperature of the devices being measured. Finally, the results of any such
extraction are limited to the specific device being measured. Thus, the entire
procedure would have to be repeated for each transistor structure and transistor type
of interest.
Another approach, which avoids the inherent complexities of thermal
measurements, is to derive the thermal impedance of a transistor from the physical
equations that govern the temperature and heat flow in the device. Physical thermal
modeling is desirable because it can give the temperature behavior as a function of
the device structure and material properties alone; therefore, the effects of device
technology scaling on the thermal impedance can be predicted. The requirements of
accurate physical modeling (e.g. multidimensional numerical simulations) tend to
conflict with the needs for simplicity and efficiency in circuit simulation. However,
a thermal impedance model does not need to be absolutely accurate to provide
reasonable results within an ETCS. Therefore, by using certain heuristic
assumptions, compact physical models for the thermal impedance, suitable for
efficient simulation, can be derived. It is important, though, that the correlation
between the accuracy of the thermal impedance models and the accuracy of the
simulated electrical characteristics of a semiconductor device in the presence of self
heating be understood.
The sensitivity of a given electrical parameter, X, of a semiconductor
device to the thermal resistance can be defined as
RTH RTH aX
sx X T (1.14)
X X .RTH
As an example, since the output current of a device is very important for
characterizing performance, (1.14) can be used to determine the sensitivity of the
collector and drain currents of BJT's and MOSFET's, respectively. Using (1.1) in the
steadystate limit and (1.6) with (1.14), the sensitivity of the collector current of a
BJT is expressed as
RTH q. (Vg VBE) .RTH P
S (1.15)
c k (RTH P + T)2
where Vg is the semiconductor bandgap voltage. A similar expression for the
sensitivity of the drain current of a MOSFET can be determined using the current
equation given by Fox and Brodsky [Fox93a], which results in
SRT RTH. p P RTH. p
SI= a + 1 (1.16)
1 To To
where a is typically between 1.5 and 1.8 (assuming that the temperature dependence
of the drain current is dominated by the temperature sensitivity of the carrier
mobility). The expected level of error in simulated output currents can be
approximated by the product of the sensitivity and the anticipated error in the thermal
impedance model. Therefore, as shown by (1.15) and (1.16), the relation between the
accuracy of the thermal impedance models and the accuracy of the calculated
electrical parameters depends on the power dissipation and the sensitivity of the
electrical parameters to temperature. Consequently, the level of accuracy of a
thermal impedance model is more critical for devices with electrical characteristics
that are highly sensitive to temperature (e.g. BJT's as opposed to MOSFET's). At
low power dissipation levels, where the temperature rise is small compared to the
ambient temperature, the error in the thermal impedance model will not directly
correspond to the error in the calculated operating temperature. For a temperature
rise of twenty degrees, the sensitivities of the BJT collector current (VBE = 0.8) and
MOSFET drain current are 0.7 and 0.1, respectively. In such a case, the error in the
electrical characteristics will tend to be lower than the error in the thermal
impedance. Whereas at large power dissipation levels, the temperature rise can be
much larger than the ambient temperature, and the error in the thermal impedance
model will directly correspond to the error in the calculated operating temperature
(for a temperature rise of onehundred degrees, the respective BJT and MOSFET
current sensitivities are 2 and 0.4); in which case, large errors in the calculated
electrical characteristics can result. Figure 1.4 shows an example of BJT
characteristics simulated assuming a 20% error in the thermal resistance model; the
simulations were performed using the modified version of SPICE created by Lee
[Lee96]. The data clearly shows that for larger temperature rises, the error in the
calculated current (due to errors in the thermal impedance model) increases.
The motivation behind this dissertation is the development of compact
thermal impedance models for semiconductor transistors. These models can provide
a reasonably accurate representation of the dynamic temperature response within a
device; more importantly, since the models depend mainly on the physical structure
of a device, they can correctly anticipate the effects of technology scaling on the
thermal behavior. Physicsbased thermal impedance models allow an ETCS to
predict dynamic selfheating effects in circuits and can also provide more accurate
electrical parameter extraction. In addition, when the thermal impedance models are
coupled with physicsbased compact device models, the combination provides an
efficient tool for studying selfheating in semiconductor transistors.
40
S30
S20
o
U 10 
0
0Figure 1.4
Figure 1.4
1 2 3 4 5
CollectorEmitter Voltage, VCE (V)
Simulated output characteristics of a BJT, assuming that
RTH = 1000 C/W, for VBE = 0.80, 0.85, 0.90 and 0.95 V. The
simulations are repeated assuming a 20% error in the thermal
resistance model, so that RTH = 800 oC/W.
1.7 Organization
Chapter Two presents a physicsbased model for the thermal impedance of
bulk junctionisolated bipolar transistors. The model is derived by solving the three
dimensional timedependent heat conduction equation in the substrate. The ability of
the model to represent bulk BJT/HBT's with either LOCOS or trench isolation is
investigated. To account for multipleemitter bipolar transistors, the thermal
impedance model is extended to represent multiple heat sources. The accuracy of the
model is evaluated using measurements and threedimensional finiteelement
simulations.
Chapter Three describes a circuit network for modeling thermal
interactions between devices located in the same substrate. The network is developed
for the specific application of multipleemitter bipolar devices, but is shown to be
valid for general crosssubstrate thermal coupling in circuits. A method for
improving the simulation efficiency of a multipleemitter BJT/HBT electrothermal
model, using a lumped thermal impedance model, is presented. The validity of the
lumped modeling approach is supported with comparisons to the full electrothermal
model.
Chapter Four presents a predictive scalable model for the thermal
impedance of BJT's with full dielectric isolation. The model is derived by solving
the threedimensional timedependent heat conduction equation in the substrate
accounting for the buried oxide and trench isolation. In the limit of steadystate heat
conduction, the thermal impedance model is simplified, resulting in a closedform
model of the thermal resistance. The accuracy of both models is evaluated using
threedimensional finiteelement simulations and measurements.
Chapter Five describes a physicsbased model for the thermal impedance
of bulk MOSFET's. The model is derived by solving the threedimensional time
dependent heat conduction equation in the substrate. The effects of the device
interconnects and isolation structures, such as LOCOS and trenches, on the thermal
impedance are investigated. The accuracy of the model is evaluated using
measurements and threedimensional finiteelement simulations.
Chapter Six presents a predictive scalable model for the thermal
impedance of SOI MOSFET's. The model is initially derived for steadystate heat
conduction by coupling separate onedimensional heat conduction analyses in the
silicon film and interconnects. The derivation is then carried out for the case of time
dependent heat conduction, resulting in a model for the dynamic thermal impedance.
The accuracy of both models is evaluated using threedimensional finiteelement
simulations and measurements.
Chapter Seven describes a computer program developed to facilitate
thermal modeling in circuit simulation. The program, referred to as the Thermal
Impedance PreProcessor (TIPP), functions as a framework for obtaining the
component values of thermal equivalent circuits from the thermal impedance models
presented in Chapters Two through Six.
Chapter Eight concludes the dissertation with a summary of the
accomplishments of this work and suggestions for future modeling efforts.
CHAPTER 2
A THREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR JUNCTION
ISOLATED BIPOLAR TRANSISTORS
2.1 Introduction
The models derived in this chapter provide closedform physical solutions
for predicting the thermal impedances for single and multipleemitter bipolar
junction (BJT) and heterojunction bipolar (HBT) transistors, based solely on device
geometry and material properties. These models can predict both steadystate and
dynamic selfheating due to the semiconductor substrate. Previous works in this area
provided values for the thermal impedance of BJT's or HBT's, but were either
limited by assumptions or relied on nonpredictive measurement techniques. For
example, the thermal impedance model derived by Fox and Lee [Fox91a] is limited
to singleemitter devices. The analyses in other works only provide models for the
steadystate thermal resistance [Lio93, Bau94, Daw94, Lio94, Lio96]. Some authors
have used measurement techniques to extract either the steadystate thermal
resistance or simple onepole approximations for the thermal impedance [Bau93,
Liu93, Daw94, Liu95a, Liu95b]; in either case, the results do not provide a complete
picture of selfheating and are not predictive.
The thermal analysis by Joy and Schlig [Joy70] serves as the foundation
for deriving of thermal impedance model, and the first part of this chapter re
examines this work to provide a clear background for modifications made to the
model later in the chapter. The thermal impedance model developed by Joy and
Schlig was derived for singleemitter, junctionisolated BJT's operating in the
forwardactive region. A diagram of a typical junctionisolated npn BJT is shown in
Figure 2.1. In this chapter, the basic model is modified to account for variations in
substrate thickness. The effects of interconnect metallization and different isolation
technologies on the thermal impedance, and thus on the performance of the model for
advanced device structures, are investigated. The singleemitter thermal impedance
model is finally extended to account for BJT/HBT's with multiple emitter fingers.
2.2 Derivation of the SingleEmitter BJT/HBT Thermal Impedance Model
For the derivation of the singleemitter bulk BJT/HBT thermal impedance
model, the semiconductor substrate is represented by a homogeneous semiinfinite
halfspace with an adiabatic top surface (no heat transfer perpendicular to the
surface). The back side of the substrate is assumed to be held at a constant
temperature, To. Since the substrate material is assumed to be homogeneous, the
model most directly applies to junctionisolated transistors. The effects of other
types of isolation structures used in bulk technologies, such as recessed LOCOS
(local oxidation of silicon) or backfilled trenches, on the thermal response are not
taken into account. Figure 2.2 illustrates the simplified device geometry assumed for
the model derivation; the diagram focuses on the "electrically active" portion of the
device that lies directly beneath the emitter stripe, which has a width W and length
Collector
psubstrate
Crosssection of a typical junctionisolated bipolar junction transistor
(BJT).
Figure 2.1
Emitter
Base
(dT/dz) = 0
__  r_ 
The simplified device geometry used to define the solution domain for
the bulk, singleemitter BJT/HBT thermal impedance model. The
substrate is represented by a semiinfinite halfspace with an adiabatic
surface (the dotted lines). The emitter stripe has a width W and length
L. The heat source (the rectangular volume) is displaced a distance D
below the surface of the device, equivalent to the depth of the base/
collector junction. The heat source has a thickness H which
approximates the base/collector spacecharge region (SCR).
D
H
Figure 2.2
L. The imbedded heat source represents the base/collector spacecharge region
(SCR), which is further represented by a rectangular volume with a thickness, H. The
heat generated in this region is assumed to be due to uniform power dissipation. This
assumption is reasonable for devices in the forwardactive region of operation prior
to any high current effects, as the current distribution in the intrinsic device will be
approximately uniform. The electric field gradient in the base/collector SCR can also
be neglected since it does not greatly affect the thermal impedance model. The heat
source is displaced beneath the surface of the substrate by a distance D, assumed to
be the depth of the base/collector junction. Thus, any encroachment of the base/
collector SCR into the base region is neglected (which is reasonable since the base
typically has a higher doping than the collector).
Representing the substrate as a semiinfinite medium presumes that the
backside and the lateral edges do not influence the thermal response of the device.
Neglecting the effects of the back side of the substrate on the thermal response is
reasonable since a typical wafer is about 1000 times thicker than the heat source.
Neglecting the effects of the lateral boundaries requires that the device be located
sufficiently far from the substrate edges; the work by Fox et al. [Fox93b] suggests
that this assumption is valid for any device that is at least a distance 5/W L from
any lateral edge. The surface of the substrate is assumed to be the only boundary that
affects the thermal response of the device and it is considered to be adiabatic; thus,
conduction through the interconnects and conduction/convection from the surface
are neglected. Ignoring thermal energy transport from the substrate surface is
supported by the work of Berger and Chai and Goodson et al. [Ber91, Goo95];
however, they were mainly concerned with transport via convection to a surrounding
gas (namely air). Nonetheless, for the regions of the device covered by oxide, it is
unclear whether there is substantial heat conduction to this overlying oxide. From the
analysis of Goodson et al. [Goo95], the devicetooxide thermal conductance is of the
order of G = 4rk, which corresponds to an isothermal disk of radius r on the
boundary of a semiinfinite medium of thermal conductivity k. Approximating the
radius as J(WL)/7t and using the roomtemperature thermal conductivity of SiO2,
the devicetooxide thermal conductance for a typical device is on the order of
1 x 106 (W/OC). Comparably, the devicetosubstrate thermal conductance is on the
order of 1 x 103 (W/C), showing that the majority of heat will flow through the
substrate.
The temperature rise at any point within the device can be described by the
nonhomogeneous threedimensional heat conduction equation
V2AT(x, y, z, t) + g(x, y, z, t) I DAT(x, y, z, t) (2.1)
k a at
and the boundary conditions
AT( y, z, t) = 0 (2.2)
AT(x, +oo, z, t) = 0 (2.3)
aAT(x, y, z, t) 0 (2.4)
z=o
AT(x, y, o, t) = 0, (2.5)
where AT is the temperature rise above the local ambient (AT = TTo), g is the
internal energy generation density, k is the thermal conductivity, a is the thermal
diffusivity (a = k/(p cp) where p is the density and cp is the specific heat) and t
is time. Typical values for the material properties are given in Table 2.1.
Table 2.1 Semiconductor material properties
Source: [Mul77]
Equation (2.1) assumes that the thermal conductivity is independent of temperature
and position. Neglecting the temperature dependence of the thermal conductivity is
reasonable for a moderate temperature rise, where the temperature rise will vary
linearly with power dissipation. However, for large temperature excursions, the
value of the thermal conductivity can vary significantly; the thermal conductivities
of Si and GaAs will vary from their roomtemperature values by more than 20%
above 355 and 390 K, respectively [Gao89]. For such large temperature excursions,
the linear relation between temperature rise and power will not be valid. However,
the temperature dependence of the thermal conductivity can be accounted for by
Parameter Si GaAs
k (W cm K1) 1.412 0.455
p (g cm3) 2.328 5.316
Cp (J g1 K1) 0.70 0.35
using the Kirchoff transformation [Joy75], as discussed in Chapter Eight. Neglecting
the spatial dependence of the thermal conductivity implies that the effect of dopant
atoms is ignored. In the works by Weber and Gmelin and Goodson et al. [Web91,
Goo95], the thermal conductivity of doped silicon (up to lx1018 and 1.7x1019 dopant
atoms cm3) above 300 K is shown to differ only slightly from that of intrinsic
silicon. Since the majority of the substrate is typically lowdoped semiconductor
material, neglecting the doping effects on the thermal conductivity is reasonable.
With the initial thermal conditions within the substrate specified as
AT(x, y, z, 0) = 0, (2.6)
the solution to (2.1) can be expressed in the form
t
AT G(x, y, z, t) dt G(x, y, z, tx', y ,t')g(x', y, z, t')dv' (2.7)
t'=0 V
where
1 (x(x) (y)y)
G(x,y,z, tx',y',zz',t') = 1 __(exp  exp (
8[to(tt')]3/2 L4(t t )J 4(t t)
exp (z') + exp ( (2.8)
4a(t j t) 4(t t )(2
is the Green's function for the given boundaryvalue problem [Ozi93]. Equation (2.8)
is the solution to
V2G + gpi (x x')8(y y')8(z z')(t t) 1 G(2.9)
k a at
for the boundary and initial conditions given by (2.2) through (2.6), and physically
represents the temperature at point (x, y, z) at time t, due to an instantaneous point
source, gp (W s), of unit strength at point (x', y', z') at time t .
To account for the heatgeneration volume (V = W L H), (2.8) is
substituted into (2.7) and integrated over the base/collector SCR, resulting in
t
SP(t') ( L/2 + x ( L/2x x
AT(x, y, z, t)= P(t erf( L/2x +erf
S8pcV \,4ac(t t) 4c((t t')
t=0
r W/2+y W/2y
[erf( W/2+ + erfW/2
L V4a(t t') ,4a(t t')
S[erf z+D+H erf( Dz_
L erf)+erf
L 4a(t t4) a4(t t))
( zD D+Hz
+ef erf +erf( D+Hzdt' (2.10)
/4a(t t) J4c(t t )
where g(x', y', z', t') = g(t') = P(t')/V, since the power dissipation is assumed to be
uniform. Equation (2.10) represents the temperature response at any point in the
device at time t due to a change in continuous power dissipation in the base/collector
SCR. Assuming a step increase in power at t' = 0 (P(t') = P U(t) ) and expressing
the temperature rise as
AT(t) = ZTH(t) P (2.11)
yields the transient thermal impedance
r 1 r (L/2 +x+ erfL/2x)]
ZTH(x, z, t) = J8p erf2 + erf( 
/2+y y /2y y
S[erf (W/ + erf /2Y
[erf( z+D+H ) D z
erf + + erfy4
+erfz +erf(+Hz dt (2.12)
where the t value of the thermal impedance corresponds to the thermal
spreading resistance RTH.
Equation (2.12) represents the temperature rise at any point in the device
normalized to a unitstep increase in power dissipation. For circuit simulation, a
single temperature is needed to represent the effective operating temperature of the
device. Fox and Lee [Fox91b] showed that the thermal impedance model evaluated
at a surface corner of the emitter (x = L/2, y = W/2, z = 0) agreed well with
measurements of the thermal spreading resistance RTH; substituting these
coordinates into (2.12) gives the following expression for the thermal impedance
1 L (W (D+H D
ZTH e) = J4 rf er erf I erf(D I Idt (2.13)
t ,4pcV 4t 4at \F4at 4atJ
In this form, the thermal impedance model has four geometric input
parameters. Of the four, three (W, L and D) are determined directly by the device
layout. However, the fourth parameter, H, depends on the operating bias of the
device. The thickness of the base/collector SCR, H, can be estimated using the
depletion approximation; assuming a onesided step junction with uniform doping on
each side gives
2 Eg 0 (VR + bi)
H = R (2.14)
q Nepi
with
kB T N
Ybi n i (2.15)
where Esi is the dielectric constant of silicon, Eo is the permittivity of free space, VR
is the reverse bias voltage on the base/collector junction, q is electronic charge, Nepi
is the doping level in the epicollector, kB is Boltzman's constant, T is temperature,
Nb is the doping level in the base, and ni is the intrinsic carrier concentration in
silicon. fbi is the builtin potential of the base/collector junction. Equation (2.14)
shows that the thermal impedance depends on the bias of the base/collector junction,
and therefore can change during device operation. However, the squareroot
dependence of H on the base/collector voltage, is relatively weak. Figure 2.3
illustrates the variation of the modeled thermal resistance with changes in the
thickness of the base/collector SCR. The three data points plotted for each simulated
device correspond to reverse bias base/collector voltages of 5, 10 and 20 V. The
largest variation is observed for the smallest device, which shows a 25% change in
its thermal resistance going from VR = 0 V to 20 V. The larger devices show a
weaker dependence on H and have no more than a 15% change in thermal resistance
30
20
10
0
150
Figure 2.3
200 250 300 350 400
Variation of H (%)
Simulations showing the effect of variations in the thickness of the
base/collector spacecharge region on the thermal impedance model
(evaluated at steadystate) for different geometry BJTs. For each
device, D = 0.35 m, Nepi = 1 x 1016 cm3 and N = 1.5 x 1018 cm3.
The yaxis corresponds to the variation between the model evaluated
at VR = 0 V and the model evaluated at VR equal to 5, 10 and 20 V.
going from VR = 0 V to 20 V. However, at high base/collector biases, the maximum
value of H becomes effectively independent of bias. As shown in Figure 2.1, typical
bipolar technologies use a heavilydoped buried layer to reduce collector resistance.
At high base/collector biases, the lowdoped epicollector region depletes down to
the buried layer; consequently, the maximum value of H should be properly limited
to the thickness of the epicollector.
2.2.1 Modification for Finite Wafer Thickness
As previously derived, the thermal impedance model for singleemitter
bulk BJT/HBT's represents the substrate as a semiinfinite halfspace. This
representation assumes that the back side of the substrate does not affect the thermal
response of the device. In general, this is reasonable since the basecollector junction
is usually within 1 pim of the substrate surface, and a typical wafer is between 350 to
800 pim thick. However, wafers are commonly backlapped to improve thermal
performance, and substrate thicknesses of 75, 80 and 100 p.m have been reported by
a number of authors [Kag94, Mar93, Liu95a]. As the wafer thickness is reduced, the
substrate can no longer be approximated by a semiinfinite medium and the effects
of the backside boundary must be taken into account.
The threedimensional Green's function in the rectangular coordinate
system can be represented by the product of three onedimensional Green's functions
G(x, y, z, tx', y', z', t') = Gx(x, tx', t') Gy(y, ty', t') Gz(z, tz', t').
(2.16)
The lateral boundaries are still assumed to extend infinitely and their effects on the
thermal response are neglected; thus, the Green's function solutions in both the x and
y directions remain unchanged. In the zdirection, however, the substrate is now
assumed to have a finite thickness Dsub. The top surface of the substrate is still
assumed to be adiabatic. The bottom surface of the substrate is assumed to be at a
constant temperature, T(Dsub) = T0, so that the temperature rise at this surface is
defined by AT(Dsub) = T(Dsub) T = 0. These boundary conditions define the
new Green's function for the zdirection, which is given by
2 2
G,(z, tz', t') = exp[ac ip(tt')] Du cos(rpz) cos(7lpz) (2.17)
sub
p=l
where lp is the set of eigenvalues for the boundaryvalue problem and are given by
the positive roots of
cos(TipDsub) = 0. (2.18)
Equation (2.18) is solved when the argument of the cosine equates to odd multiples
of t/2. Using equations (2.17), (2.16), (2.11) and (2.7), and then integrating over the
base/collector SCR, assuming a unitstep increase in power at t = 0, gives the
following expression for the thermal impedance at any point in the device
Sdtr L/2+ x L/2x
ZTH(x, y, t) = ] erf  + erf
t 4pcV 4ot ) 4a t
F (W/2+y\ (W/2yi
erf W/2 + erf(/2 y
2cos(rOpz)exp(arpt)
= pf 71PDS~b
p=1 pDsub
{sin[qlp(D + H)] sin[T[pD]} (2.19)
where V = W L H and
(2p 1) (2.20)
4 = 2D (2.20)
2sub
Evaluating (2.19) at the coordinates (x = L/2, y = W/2, z = 0) to give a single
effective operating temperature, results in the following expression for the thermal
impedance
7 dt (4L W ( )
ZTH(t) = erf( L rf(W
TH M 4pcV F4 (t 4att
2
S2exp(a0rl t)
S p Dsub { sin [rp(D+ H)] sin [lpD]} (2.21)
p= sub
Since (2.21) is derived from the physical heat conduction equation, it can
be used to anticipate the effects of substrate scaling on the thermal impedance.
Figure 2.4 illustrates equation (2.21) evaluated at various values for Dsub. The
results show that the thermal resistance decreases as the substrate thickness is
reduced, which agrees with the trend predicted by Hattori et al. using a three
dimensional numerical simulator [Hat95]. Figure 2.4 also shows that (2.13) provides
675
650
625
600
575
550
525
500
400
500
Simulations showing the effect of substrate thickness on the thermal
impedance model (evaluated at steadystate). The model accounting
for finite substrate thickness is compared to the model assuming
infinite substrate thickness. The device specifications are L = 4 9m,
W = 1 jim, D = 0.35 pm, H = 0.35 im.
200 300
Substrate Thickness, Dsub (Pm)
Figure 2.4
0.
I 0G OModel w/finite Dsub
Model w/infinite Dsub
I I I
an accurate prediction of the thermal resistance over most of the range of substrate
thicknesses: only when the substrate thickness is significantly reduced (< 100 itm),
is there a large deviation between the two models.
2.2.2 Effects of Interconnect Metallization on the Thermal Impedance
For the derivation of the BJT/HBT thermal impedance model, the surface
of the substrate is assumed to be adiabatic. In actual devices, portions of the base,
collector and emitter regions are in direct contact with the metallization used to
electrically connect different devices on a chip. Since the metallization typically has
a high thermal conductivity, it is possible that the heat conduction via the
interconnects significantly influences the thermal response of a device. Therefore,
the validity of such an assumption should be investigated.
Threedimensional (3D) finiteelement (FE) thermal simulations of a
bipolar transistor, using the ANSYS software package [Ans96], were performed to
examine the effects of the interconnect metallization on the thermal impedance. To
simplify the FE model, the device was considered to be symmetric in both lateral
directions; therefore, only one quarter of the device was simulated. The bottom and
exterior sides of the substrate were assumed to be at a fixed ambient temperature. The
top and side surfaces of the interconnects, as well as the top surface of the interlayer
dielectric, were assumed to be adiabatic. The FE simulations tend to overpredict the
heat conduction through the interconnects since any contact resistances at the
material interfaces were neglected. The assumed symmetry of the device implies that
the base and collector metallization are equidistant from the emitter. In typical
devices, the collector contact is offset a greater distance from the emitter than the
base contact. Typical ranges for these offsets are 0.5 to 10 urn between the base and
emitter contacts, and 2.5 to 25 Lim between the collector and emitter contacts
[Gra93]. While the FE model does not exactly represent any actual device structure,
it can provide an estimate for the significance of the heat flow through the
interconnects as a function of their distance from the active device.
Figure 2.5a shows the FE model for bipolar devices with full
metallization. Steadystate thermal simulations were run for various interconnect
spacings; this spacing corresponds to the edgetoedge distance between the emitter
and base/collector interconnects. Simulations were also run of the same structure
with the base/collector interconnect removed. The results of the two groups of
simulations were compared to determine the effect of the base and collector
interconnects on the thermal resistance. Figure 2.5b shows the results of the
comparison between the FE simulations. The data clearly shows that the effect of the
base/collector interconnect metallization is small and decreases as the interconnects
are moved away from the active device area. The collector interconnect has less of
an effect on the thermal impedance than the base interconnect, due to the larger
distance between the collector contact and the active device. In any case, the effect
of either the base or collector interconnect should be negligible compared to the
influence of the emitter metallization.
To determine the extent of the effect of the emitter interconnect on the
thermal impedance, steadystate thermal simulations were run for different devices
with only the emitter metallization in contact with the device. Figure 2.6a shows the
2.5
2.0
r
c3
S1.5
E
 1.0
r
o
i 0.5
0.0
Interconnect Spacing (tm)
Figure 2.5
ANSYS simulations showing the effect of emitter, base and collector
interconnects on the thermal resistance. The device specifications are
D = 0.2 pim and H = 0.35 jIm, the interconnect width Wmet = 2 pmr
and thickness diet = 0.9 [tm, and the interlayer dielectric thickness
dox = 0.7 gim: a) The finiteelement model simulated with ANSYS; b)
the variation between the thermal resistance accounting for emitter,
base and collector interconnects and the thermal resistance accounting
for only the emitter interconnect, plotted as a function of the spacing
between emitter and base/collector interconnects.
50 100
50 100
Variation of Parameter (%)
(b)
200
250
ANSYS simulations showing the effect of the emitter interconnect on
the thermal resistance for variations in different technology
characteristics. The specifications for the nominal device are
L = 4 pm, W = 1 pm, D = 0.35 pm, H = 0.35 pm, dmet = 0.9 Im,
dox = 0.9 pm and Wmet = 2 [m: a) The finiteelement model
simulated with ANSYS; b) the variation between the thermal
resistance accounting for the emitter interconnect and the thermal
resistance neglecting the emitter interconnect. The variation plotted on
the xaxis corresponds to the deviation of each structure parameter
from its nominal value.
30
25
.)
U
S20
S15
.C
H
.E 10
c
5 5
0
0
Figure 2.6
nominal
SOdmet
a dox
OD
AL
Wmet
o0 A
AA
a/
^ ^
FE model for devices with only the emitter metallization. The same devices were also
simulated with the emitter interconnect removed. The simulations were performed by
independently varying each structure parameter of the FE device model. Reasonable
values were chosen for each parameter to represent a nominal device design; each
parameter was varied about the nominal value to represent a reasonable range of
technology scaling. Figure 2.6b shows the results of the FE simulations. The emitter
metallization becomes a more effective path for heat evacuation as the thickness,
dmet, and the width, Wmet, of the interconnect increase and as the thickness, dox, of
the dielectric layer between the substrate and the interconnect decreases. The data
also show that the effect of the emitter interconnect increases as the depth of the base/
collector junction is decreased (the heat source is moved closer to the surface) and
as the length of the emitter is decreased.
Transient thermal simulations of the FE model in Figure 2.6a were used to
examine the effect of the emitter interconnect on the transient thermal response.
ANSYS was used to simulate the structure with and without the emitter interconnect
in contact with the device; the results are shown in Figure 2.7. The thermal responses
for the device with and without the interconnect match until significant heat reaches
the surface of the device. The time for heat to reach the surface of the device can be
approximated as the square of the distance D divided by the thermal diffusivity of
the substrate material. The resulting time is approximately 0.44 nanoseconds, which
agrees with the FE simulations. The adiabatic boundary condition of the device
without the interconnect predicts a larger response since the heat is completely
reflected once it reaches the surface. The device with the emitter metallization, which
1.5
U
0

1.0
S0.5
[
0.0
1C
Figure 2.7
1010 108 106 104 102
Time (sec)
ANSYS simulations showing the effect of the emitter interconnect on
the transient thermal impedance. The specifications for the device
structure are L = 2 pm, W = 1 im, D = 0.2 jim, H = 0.35 gim,
dmet = 0.9 gm, dox = 0.7 gm and Wmet = 2 im.
acts as a separate heat sink path, has a reduced thermal impedance and an effectively
slower thermal response.
Based on the results of the 3D FE simulations, neglecting the base and
collector interconnect metallization in the model derivation is reasonable since it
only slightly affects the thermal impedance of a device. The emitter interconnect,
however, has a greater influence on both the steadystate and transient thermal
responses. The effect on the thermal resistance will be more significant for devices
with smallgeometry emitters and shallow base regions, where the transient thermal
response will mainly be affected for large devices with substantial contact structures.
In either case, equations (2.13) and (2.21) will tend to overpredict both the steady
state thermal resistance and the transient rise of the thermal impedance.
2.2.3 A Model for the Thermal Impedance of the Emitter Interconnect
As shown in the previous section, the assumption that the top surface of
the device is adiabatic neglects heat flow in the emitter interconnect and results in a
thermal impedance model that overestimates the transient temperature rise in a
bipolar device. To model the effects of the emitter interconnect on the overall
thermal impedance, both the thermal resistance and thermal capacitance of the
metallization need to be considered.
The thermal resistance of the emitter metallization is derived by assuming
that the interconnect can be represented by a onedimensional cooling fin, so that the
temperature rise at any point xmet along the interconnect,
ATmet(xmet) = Tmet(xmet) To, can be approximated by
m2ATmet 2
2 mmetATmet 0.
aXmet
(2.22)
The second term on the lefthand side of (2.22) accounts for heat conduction through
the underlying oxide as the heat travels along the interconnect, where
1 kmetdmet
mmet hmet
(2.23)
is the characteristic thermal length in the interconnect and
h = kox
met d
ox
(2.24)
is the heat transfer coefficient from the interconnect to the substrate. The material
properties for the emitter interconnect are given in Table 2.2.
Table 2.2 Emitter interconnect material properties
Source: [Ozi93]
* Assumed to be aluminum
Property Definition Value
kmet Thermal conductivity 2.39 (W cmI K)
Pmet Density 2.7 (g cm3)
Cpmet Specific Heat 0.9 (J g' K)
Approximating the temperature in the interconnect using a onedimensional equation
implies that the temperature gradients in the vertical and lateral directions within the
emitter interconnect are negligible. The validity of such an assumption can be
evaluated using the Biot number, which corresponds to the ratio of the internal and
external thermal resistances of a given object [Ozi93]. If the Biot number for the
interconnect is much less than unity, then the interconnect can be approximated as a
onedimensional thermal medium. The vertical and lateral Biot numbers for the
emitter interconnect are given by Bvmet = hmetdmet/kmet and
BLmet = hmetWmetetdmetmet), respectively. For most practical metallization
geometries, the Biot numbers are much less than one and the coolingfin model is an
accurate representation of the emitter interconnect.
Assuming that the temperature rise in the interconnect at the emitter
contact is equal to the effective operating temperature of the device, and that the
temperature rise approaches zero far from the contact, the thermal resistance of the
emitter interconnect can be expressed as
RTHmet [kmetmmetmtet]et (2.25)
The thermal capacitance of the emitter metallization can be approximated as
CTHmet PmetCpmetVmet. (2.26)
The volume of the metallization is Vmet = W L met, where 5met represents the
effective length of the interconnect structure. The parameter 5met should be
evaluated to include the volume of the contact and interconnect metallization but can
also be extracted from transient thermal measurements or numerical simulations.
Once the thermal resistance and thermal capacitance have been calculated, the
transient thermal impedance of the emitter interconnect can be approximated by
ZTHmet(t) = RTHmet[l exp t (2.27)
1 .Tmet '
where Tmet = RTHmetCTHmet. The overall thermal impedance of a bipolar device can
now be represented by the parallel combination of two thermal impedances, such that
effectively
ZTHdev(s) ZTHmet(S)
ZTH(S) = (2.28)
ZTHdev(s) + ZTHmet(S)'
where ZTHdev(s) is determined from the transient thermal impedance given by either
(2.13) or (2.21).
2.2.4 Effects of Isolation Structures on the Thermal Impedance
While junctionisolated technologies are still used, the drive to increase
packing density, improve lateral isolation and increase device operating speeds has
led to the development of newer isolation technologies for VLSI bipolar applications.
The advanced isolation technologies typically used in bulk bipolar fabrication are
recessed LOCOS (local oxidation of silicon) and Ugroove [Wol90, Gra93];
Figure 2.8 illustrates examples of bipolar devices fabricated with these isolation
techniques. Since advanced isolation structures typically use low conductivity
Collector
psubstrate
(a)
Base Emitter Collector
Oxide p \ Oxide
INE 1 N
N,
psubstrate
Crosssections of typical BJT's fabricated with advanced isolation
technologies: a) Recessed LOCOS; b) Ugroove isolation.
Figure 2.8
Emitter
Base
materials like SiO2, the thermal impedance of a device using such isolation tends to
be higher than that of its junctionisolated counterpart. The bulk BJT/HBT thermal
impedance model treats the substrate as a homogeneous material; therefore, it is
unclear whether the thermal impedance model is applicable to devices which are
fabricated with advanced isolation.
Threedimensional (3D) finiteelement (FE) thermal simulations, using
ANSYS, were performed to examine the effects of advanced isolation structures on
the thermal impedance of bipolar transistors. Two FE models were developed to
separately investigate the effects of recessed LOCOS and Ugroove isolation. To
simplify the FE models, the device was considered to be symmetric in both lateral
directions, so that only one quarter of the device was simulated. The bottom and
exterior sides of the substrate were assumed to be at a fixed ambient temperature. The
top surface of the device was assumed to be adiabatic. Due to the assumed symmetry,
the active device region was surrounded on all sides by the isolation structure, which
was at uniform distance from each side of the emitter. As shown by the illustrations
in Figure 2.8, the distance between the isolation structure and the intrinsic device is
not uniform on all sides of the device. Typical values for the distance between the
emitter and the isolationfor the portions of the isolation structure immediately
surrounding the emitterare in the range from 0.3 ptm to 0.8 p.m for advanced bipolar
devices [Del91, Klo93, Yam93, Pru94]. The distance between the emitter and the
portion of the isolation structure on the far side of the collector contact is generally
larger, typically two to four microns [Del91, Klo93]. For both FE models, the side
walls of the isolation structures were perpendicular to the top surface of the substrate.
For typical Ugroove isolation, the trench is created by anisotropic etching and the
sidewalls are nearly perpendicular to the surface. However, actual LOCOS
structures have tapered edges (see Figure 2.8) that get progressively thinner toward
the active device. To determine the implications of the model's nonphysicality, two
dimensional (2D) FE simulations were run for various angles (30 to 90 degrees)
between the substrate surface and the sidewall of the isolation. The simulations
showed that the temperature rise increased as the angle increased; thus, the 3D
LOCOS model should show a larger effect than that of an actual isolation structure.
While the finiteelement models do not truly represent the physical device layout,
they allow an orderofmagnitude estimate for the effects of the isolation structures
on the thermal impedance.
Steadystate thermal simulations were run for various deviceisolation
spacings, corresponding to the edgetoedge distance between the emitter and the
isolation structure. For the Ugroove isolation model, this spacing is the distance
between the emitter and the edge of the surface LOCOS; the actual trench is assumed
to be an additional 0.5 pm away from the edge of the LOCOS [Del91, Yam93].
Simulations were also run for the same devices with the isolation structures removed.
LOCOS isolation is formed by selectively oxidizing regions of the
semiconductor substrate in a dry or wet oxygenrich ambient. For bipolar
technologies, the resulting Si02 structures are typically no more than one micron
thick, since the growth of thicker oxides is impractical [Wol90, Gra93]. Figure 2.9a
illustrates the FE model for bipolar devices with recessed LOCOS isolation. The
oxide was assumed to be fully recessed beneath the top surface of the substrate and
0 0.5 1.0 1.5 2.0 2.5 3.0 3
DeviceOxide Spacing (Lim)
ANSYS simulations showing the effect of recessed LOCOS isolation
on the thermal resistance. The device specifications are L = 2 inm,
W = 1 rim, D = 0.35 jim and H = 0.35 jim: a) The finiteelement
model simulated with ANSYS; b) the variation between the thermal
resistance accounting for the isolation and the thermal resistance
assuming a homogeneous substrate, plotted as a function of the edge
toedge spacing between the emitter and the isolation.
Odfox = 1.0 lOm
30
20
C;
E
.2 10
O
.0
0
Figure 2.9
I 1 I 1 1 1 I I I
had a thickness, dfox, of one micron. Figure 2.9b compares the FE simulations with
and without the isolation. The effect of the LOCOS can be significant at small
deviceisolation spacings, but decreases as the isolation is moved away from the
active device region. In Figure 2.8a, the portions of the LOCOS structure close to the
emitter have the largest effect on the thermal response, since they directly restrict the
lateral heat flow away from the device. A number of manufacturers are using thinner
standard or semirecessed LOCOS (0.3 to 0.6 gim) combined with junction isolation
to reduce fabrication times and improve compatibility with existing MOS
technologies [Klo93], [Pru94]. The thinner oxides have a smaller effect on the
thermal resistance, and therefore, the FE simulations can be considered worstcase.
Ugroove isolation differs from LOCOS in that trenches are etched
directly into the substrate and then backfilled with oxide and polysilicon. The depth
of the trench, dtr, is typically on the order of 3 pim [Yam93, Ona95], but has been as
large as 5 ptm [Del91]; the width of the trench is generally in a range from 0.6 to
1.5 pim [Del91, Yam93, Ona95, Shi96]. Ugroove trenches will typically have a
surface LOCOS layer, but the thickness of this layer is usually no greater than 0.1 to
0.15 jim [Yam93], since the isolation is mainly achieved by the trench. Figure 2.10a
shows the FE model for devices with Ugroove isolation. The thickness of each fill
layer (dtrox for oxide and dpoly for polysilicon) in the Ugroove was assumed to be
uniform. Figure 2.10b compares the FE simulations with and without the isolation.
The effect of the Ugroove isolation on the thermal resistance is greater for small
deviceisolation spacings than in LOCOS due to the larger depth of the trench.
0.5 1.0 1.5 2.0 2.5
DeviceIsolation Spacing
3.0
(pm)
3.5 4.0 4.5
Figure 2.10
ANSYS simulations showing the effect of Ugroove isolation on the
thermal resistance. The device specifications are L = 2 tm,
W = 1 pm, D = 0.35 pim and H = 0.35 p.m. The Ugroove
specifications are dtr = 3.5 Jm, dtrox = 0.38 pm and dply = 0.75 pm:
a) The finiteelement model simulated with ANSYS; b) the variation
between the thermal resistance accounting for the isolation and the
thermal resistance assuming a homogeneous substrate, plotted as a
function of the edgetoedge spacing between the emitter and the U
groove isolation.
60
50
, 40
CZ
E 30
.
.5 20
0
' 10
c>
IIIIIIIII
However, these results represent the worst case, since in an actual device the active
region is not immediately flanked by the Ugroove on all sides.
Transient thermal simulations of the FE models shown in Figure 2.9a and
Figure 2.10a were used to examine the effects of both LOCOS and Ugroove
isolation on the transient thermal response. ANSYS was used to simulate the device
with and without the isolation structures; the results are shown in Figure 2.11. As the
heat travels laterally and reaches the edges of the isolation structure, the response
accounting for the isolation begins to deviate from the response without the isolation.
The time for the heat to reach the edges of the isolation structures can be
approximated as the square of the deviceoxide separation (1 jtm) divided by the
thermal diffusivity of the substrate material; the resulting time is on the order of ten
nanoseconds, which agrees with the simulations of both the LOCOS and Ugroove
isolation. The oxide used in the isolation structures restricts the lateral flow of heat
away from the device and in both cases results in a larger temperature rise.
Based on the results of the 3D FE simulations, advanced isolation
structures such as recessed LOCOS and Ugroove can considerably increase the
thermal impedance of bipolar devices. In most cases, the bulk bipolar model will tend
to underpredict both the steadystate and transient thermal response of devices
fabricated with oxidebased isolation structures. The error in the model will be the
greatest for advanced, highlyscaled devices fabricated with deep trench isolation.
102
Time (sec)
(a)
102
Time (sec)
Figure 2.11
ANSYS simulations showing the effect of advanced isolation
structures on the transient thermal impedance. The deviceisolation
spacing is one micron. The specifications for the device structure are
L = 2 rim, W = 1 rim, D = 0.35 ptm and H = 0.35 gim: a) Recessed
LOCOS or BOX isolation with dfox = 1.0 prm; b) Ugroove isolation
with dtr = 3.5 pLm, dtrox = 0.38 lim and dpoly = 0.75 pm.
2.3 Verification of the SingleEmitter Thermal Impedance Model
To verify the thermal impedance model, threedimensional (3D) finite
element (FE) simulations of a junctionisolated BJT were performed using ANSYS.
Interconnect metallization was neglected and the substrate was assumed to be
homogeneous silicon with the bulk properties given in Table 2.1. The FE simulations
were evaluated at the surface corner of the emitter and compared to the singleemitter
thermal impedance model given by equation (2.21); the results are shown in
Figure 2.12. The analytic model agrees closely, for both the steadystate and the
transient, with the 3D FE simulations for both device geometries. The predicted
values for the steadystate thermal resistance agree within twelve percent of the FE
simulations. The error can be partially attributed to numerical error associated with
the FE mesh.
The model was also compared to measured thermal impedances. The
measured data were extracted using the basethermometry technique developed by
Zweidinger et al. [Zwe96]. Figure 2.13, Figure 2.14 and Figure 2.15 compare the
measured and simulated data for the transient thermal impedance of Harris HBC bulk
BJTs. The thermal impedance model does a good job of predicting the steadystate
thermal resistance, with no more than a 20% error between the model and the
measurements. The model given by (2.13) tends to overpredict the transient
response. As shown with the ANSYS simulations in Figure 2.7, this discrepancy can
be attributed to the model's neglect of the emitter metallization. When the thermal
impedance of the emitter interconnect is accounted for, with 5met = 50 pim extracted
TEMPERATURE (C):
I I
27
27,431
27.863
28,294
28.725
29,157
29.588
30,019
30.451
30,882
Time (sec)
(b)
Figure 2.12 The transient thermal impedance simulated with ANSYS and
calculated with the bulk, singleemitter model: a) The finiteelement
model simulated with ANSYS for P = 1.8 mW; b) comparison of
thermal impedances simulated with ANSYS (symbols) and the thermal
impedance model (lines).
1150
950
750
550
350
150
50
1
10"
Time (sec)
~'50
U
0
E40
~30
 20
E
0
102
102
10u
Time (sec)
Figure 2.13
Measured and
Harris HBC
L = 100 tm.
simulated data for the transient thermal impedance of
bulk BJT's with W = 2 m: a) L = 30 m; b)
300
220
140
60
106
Time (sec)
20
102
Time (sec)
Figure 2.14
Measured and simulated data for the transient thermal impedance of
Harris HBC bulk BJT's with W = 3 4im: a) L = 10 itm; b) L = 30 pim.
260
220
180
140
100
60
20
102
Time (sec)
102
Time (sec)
Figure 2.15
Measured and simulated data for the transient thermal impedance of
Harris HBC bulk BJT's with W = 5 ptm: a) L = 10 pnm; b) L = 30 pm.
from the measurements, the model provides a more accurate representation of the
transient thermal response.
2.4 Derivation of the MultipleEmitter BJT/HBT Thermal Impedance Model
The thermal impedance model for bulk MEBJT/MEHBT's is an extension
of the singleemitter model. A multipleemitter device consists of singleemitter
devices placed adjacent to each other along their lengths. Since there are multiple
devices (referred to as "emitter fingers") that are thermally coupled through the
substrate operating in close proximity, the temperature rise in each emitter finger is
affected not only by its own power dissipation, but also by the power dissipated by
its neighbors. The heat conduction equation, (2.1), is linear, so superposition can be
used to calculate the total temperature rise in the device. The equation for the
temperature rise can then be manipulated to provide expressions for the effective
temperature rise in each individual finger.
Figure 2.16 illustrates the simplified multipleemitter device geometry
assumed for the model derivation. The substrate is represented by a homogeneous
semiinfinite halfspace with an adiabatic top surface with multiple imbedded heat
sources. The emitter fingers are assumed to be uniform in size and shape, with width
W and length L. Each finger has a corresponding heat source, due to an assumed
uniform power generation in the base/collector SCR; each heat source has a thickness
H and is displaced a distance D below the surface of the substrate. As with the
singleemitter model, D is assumed to equal the depth of the base/collector junction
W K"1
Figure 2.16
The simplified device geometry used to define the solution domain for
the bulk, multipleemitter BJT/HBT thermal impedance model. The
substrate is represented by a semiinfinite halfplane with an adiabatic
surface. Each emitter finger has a width W and length L and each heat
source (the rectangular volumes) is displaced a distance D below the
surface of the device and has a thickness H. The distance D is
equivalent to the depth of the base/collector junction and the thickness
H is approximated by the thickness of the base/collector SCR. The
emitter fingers are uniformly spaced with and edgetoedge separation
distance S.
and H can be calculated using equations (2.14) and (2.15). The edgetoedge
separation, S, between adjacent fingers is assumed to be uniform.
The Green's function technique can be employed to find the temperature
rise within the device. By applying superposition, the solution is expressed as the
sum of the Green's function solutions for the multiple heat sources
n t
AT(x, y, z, t) = J dt' G(x, y, z, tx', y', z', t')g(x', y', z, t')dv'. (2.29)
1 t =0 V
where G(x, y, z, tx', y', z', t') is given by equation (2.8). The summation accounts for
the integration over the different spatial coordinates of each heat source. To clarify
the derivation, certain conventions and definitions can be established. The origin for
the coordinate system is fixed at the center of the leftmost finger at the surface of
the device. A device is considered to have a total of n emitter fingers and a reference
order is established with the fingers numbered sequentially starting from the left
most finger. The character j, where j = 1 > n, is used to reference a specific emitter
finger. The ith neighbor (where i = i > n 1) of a given emitter finger, EFj, is
defined as a finger situated an edgetoedge distance [iS + (i 1)W] away on either
side. Using equations (2.8) and (2.29), the temperature rise at any point in the device
assuming a step increase in power at t = 0 for each fingeris given by
n ^P v dt .(L/2 + x erf(L/2 x
AT(x, y, z,t) = 8V[e[ () erf J
S[erf( (2j3)W/2 (j 1)S
+ erf(y+(2j1)W/2+(j 1)S']
/(xti
[r z+D+H Dz
erf +D+H + erf(z
(zD) D+Hzcl
+ erf +erf (2.30)
which accounts for n heat sources, one for each emitter finger EFj.
Equation (2.30) can be manipulated to provide the temperature rise in each
emitter finger. As with the singleemitter model, the temperature rise in each finger
is represented by a single effective value. To simplify the derivation, symmetry is
assumed such that the distance from the effectivetemperature point of finger EFj to
the heat source of its i th neighbor, is the same as the distance from the effective
temperature point of the ith neighbor to the heat source of EFj. This symmetry is
attained only for the coordinates (x, y = [j I ][S + L], z). When (2.30) is evaluated
at each of these points, the model is reciprocal and the effective temperature rise in
each emitter finger, ATEFj, can be expressed as
ATEFI ZS ZCI ... ZC(n 1) P
ATEF2 ZC Zs ... ZC(n 2) P2
ATEFn ZC(nl) ZC(n 2) S Pn (2.31)
where Zs is referred to as a self impedance and ZCi is the i th coupling impedance.
The system of equations given by (2.31) shows that the temperature rise
in each finger is determined by the power dissipation in its own heat source and by
the power dissipated in the (n 1) neighboring heat sources. The self impedance is
given by
v dt (L/2 + x. (L/2 x W/2
Zs(x, z, t) = erf + erf erf
I t 4pcV at at J t
j=It
z[erf(+D+H + Dz
+ erf + erf 
/4c4ct /4at 
erf + erf (D  (2.32)
and accounts for the portion of the temperature rise in a finger due to that finger's
own power dissipation. The ith coupling impedance can be expressed as
Sf dt r fL/2 +x erfL/2x
Zc(x, z, t) =  [erf, +erf 4
j=lt
cJ It 8pcV ( J4xt ) ( /4xt
rf (W/2 + i(W+S)) (W/2 i(W + S))+
e F4at /4 ct
erf ++H + erf( >z
( 14at ) \ /4Tt )
+ erf + e D+rHz (2.33)
,4(t^ J4axt )]
and accounts for the portion of the temperature rise in a finger due to the power
dissipated by its ith neighbor. Thus, for the assumed symmetry, the thermal
impedance of a device with n emitter fingers can be described with a single self
impedance and (n 1) coupling impedances.
Equations (2.32) and (2.33) should be evaluated at a single point to
represent the temperature rise of each finger by a single effective value. To keep the
MEBJT/MEHBT model as similar as possible to the singleemitter model, the points
x = L/2 and z = 0 are used, giving
r ( L ^ CW/2 > (D+ H> D 'Ni
(t = erf rf W2 erf erf dt (2.34)
Zs(t) = 2pcV 4t 4tA) 4(t y4 dt
t 24 pV At f4 (xat J4at /at
and
ZCi(t) = p erf i
Zc 4pcV t4t cv t
[erf (W/2 + i(W + S)) ef(W/2 i(W +S))
erf 4et (2.35)4t
erfD+Herf( D dt (2.35)
L 4at ) 14xt
as the final expressions for the self and coupling impedances. Therefore, the overall
selfheating on the scale of the entire device can be described by the selfheating and
thermal interactions on the smaller scale of each individual emitter finger.
Accounting for a finite wafer thickness can be important for multiple
emitter devices since the coupling impedances decrease as the wafer thickness is
reduced [Daw94], [Hat95]. The multipleemitter model can be modified in a similar
fashion as that for the singleemitter model; by simply using equations (2.17) and
(2.20) in place of the Gz(z, tlz', t') in equation (2.29), the expressions for Zs and Zci
will now account for a finite wafer thickness. Since the multipleemitter thermal
impedance model is simply an extension of the singleemitter model, the effects of
interconnect metallization and advanced isolation technologies are not taken into
account. Neglecting these portions of the overall device structure is assumed to affect
the multipleemitter model in the same manner, and to the same extent, as to which
it affects the singleemitter model.
2.5 Verification of the MultipleEmitter Thermal Impedance Model
Twodimensional (2D) finiteelement (FE) simulations of a junction
isolated, threefinger BJT were performed using ANSYS to verify the multiple
emitter thermal impedance model. Twodimensional FE simulations were used
instead of 3D simulations due to limitations of the available version of ANSYS. The
validity of comparing 2D FE simulations to a 3D analytic model is established by
evaluating the thermal impedance model derived for both two and three dimensions.
Figure 2.17a compares the results, which show that the 3D the 2D models converge
for long devices. The difference in the predicted thermal resistance values decreases
from 22% to less than 1% as the length of the device is increased from 50 pim to
800 ptm. Consequently, the 2D FE simulations can verify the 3D thermal
impedance model evaluated for devices with long emitters. The 2D FE simulations
do not verify the model for shorter devices where the heat flow becomes three
dimensional. However, the verification of the singleemitter thermal impedance
model for 3D heat flow can be assumed to also verify the MEBJT model. This
assumption is reasonable since the physics that describe the singleemitter model
also apply to the MEBJT thermal impedance model.
The physical device was assumed to be symmetric so that the FE model
represented only half of the device. Figure 2.17b shows an illustration of the FE
model simulated with ANSYS. Interconnect metallization was neglected and the
substrate was assumed to be homogeneous silicon with the bulk properties given in
Table 2.1. The bottom and exterior side of the substrate were held at a constant
ambient temperature while the top surface and the interior side were assumed to be
adiabatic. The FE simulations were compared to the multipleemitter thermal
impedance model given by equations (2.34) and (2.35), accounting for a finite
substrate thickness; the results are shown in Figure 2.18. The analytic model agrees
well, in both the steadystate and transient, with the 3D FE simulations of the self
and coupling impedances. The predicted values for the steadystate thermal
resistance agree within three percent of the FE results, which is within the expected
error of the model and the numerical simulations.
74
250
S GO2D Model: L = 50 pm
U 200 03D Model: L = 50 pm
0. 3 2D Model: L = 200 gm O 
S E 3D Model: L = 200 m
AA2D Model: L = 800 pm
150 A3D Model: L = 800 gm
S100 
E
I / ,^ B B
50 
0 3 ,,, ._ 
0f Qs .^ 'A""
1012 1010 108 106 104 102 100
Time (sec)
(a)
TEMPERATURE (oC):
27
i 29,072
31.145
33,217
35.289
S1I 37,361
39.434
41,506
43.578
45,651
(b)
Figure 2.17 Twodimensional heat flow in multipleemitter bipolar transistors: a)
A comparison of the threedimensional thermal impedance model to a
twodimensional model for W = 1 im, D = 0.5 pim and H = 0.5 grm;
b) the finiteelement model simulated with ANSYS for P = 500 pW.
15 r ,
OZs: 2D ANSYS Al A A AA
[ OZcl: 2D ANSYS
UA
o AZs+Zc2: 2D ANSYS 0 0 0 00
10  Zs: Model
S  ZCI: Model
a  Zs+Zc2: Model
E 5
0 /
1012 1010 108 106 104 102
Time (sec)
(a)
8
_ _0_ _A A_ A4a
OZs: 2D ANSYS O O O O GD
oZci: 2D ANSYS
o 6 AZs+Zc2: 2D ANSYS
S Zs: Model
T  Zci: Model
S ZS+Zc2: Model
Q 4
r/
0 ii
1012 10 0 10 106 104 102
Time (sec)
(b)
Figure 2.18 The transient thermal impedance simulated with ANSYS and
calculated with the bulk, multipleemitter model for L = 500 pm and
S = 1 (im: a) W= 1 (im, D =0.2 pLm, H =0.3 im; b) W = 3 pm,
D = 0.5 tim, H = 0.5 pm.
2.6 Summary
A thermal impedance model for bulk singleemitter BJT/HBT's was
presented and then extended for devices with multiple emitter fingers. The model
was shown to agree reasonably well with threedimensional finiteelement
simulations and measurements of junctionisolated devices. The effects of
interconnect metallization and advanced isolation technologies on the thermal
impedance were investigated; a simple model for the thermal impedance of the
emitter interconnect was demonstrated. The results suggest that the model can be
expected to provide reasonable predictions for the thermal impedance of junction
isolated devices. However, for highlyscaled devices, the effects of advanced
isolation can be significant and the accuracy of the model will decline. Methods for
modeling the effects of isolation structures are proposed in Chapter Eight.
CHAPTER 3
A CIRCUIT MODEL FOR THERMAL COUPLING AND A LUMPED
ELECTROTHERMAL MODEL FOR BULK MULTIPLEEMITTER BIPOLAR
TRANSISTORS
3.1 Introduction
Due to increased interest in the role of thermal effects in device and circuit
operation, especially for silicononinsulator (SOI) and heterojunction technologies,
circuit simulators and compact device models have been modified to account for the
dynamic temperature response within a device [McA92, Fox93b, Fos95]. Most of the
implementations have been applied to the case of selfheating, where a device's
effective operating temperature (EOT) depends on its power dissipation only. In
many circuits and some devices, such as multipleemitter bipolar transistors, a
number of devices can operate in close proximity. Under such conditions, the EOT
of a device is no longer determined solely by its own power dissipation but also
depends on the operation of its neighbors. Therefore, not only must circuit simulators
(and compact device models) be able to model dynamic selfheating, they must also
be able to model the dynamic thermal coupling between individual devices or
portions of one device.
An approach for modeling crosschip thermal coupling using a circuit
simulator was described by Fukahori and Gray [Fuk76]. The thermal coupling
between devices in an arbitrary circuit was modeled using a finite difference
technique. The semiconductor substrate was represented by a threedimensional
numerical mesh with equivalent thermal resistances and capacitances. The electrical
elements in the circuit (transistors, etc.) were represented by their standard compact
circuit models. The values for the lumped thermal components were calculated by
discretizing the heat conduction equation using a finite difference approximation. In
[Mar93], a similar approach was presented and applied to the simulation of multiple
emitter HBT's. In this case, twoport theory was used to generate a finite twodimensional
resistance network that represented steadystate heat conduction in the substrate. For both
applications, the resulting circuit admittance matrix contained elements corresponding to
the electrical circuit and also the thermal elements. The NewtonRaphsonlike iteration
scheme of the modified circuit simulators was then used to solve the coupled electrothermal
problem. To simulate both interdevice thermal coupling and selfheating using this
method, a large number of thermal nodes is required; therefore, this approach can
drastically increase simulation time.
Chapter One described a common method for using thermal impedances
to efficiently model selfheating in circuit simulators. A logical progression would
be to expand this method to account for thermal coupling between devices. Such an
approach can provide a more efficient alternative to the seminumerical methods
mentioned above. This technique was applied by Moinian et al. for modeling cross
substrate thermal coupling in bipolar circuits [Moi94], and by Baureis for modeling
multipleemitter HBT's [Bau94]. However, their circuit implementations did not
correctly represent the thermal interactions between (or within) the devices. The
shortcoming of the coupling model used in these works is discussed in this chapter.
A circuit model is then presented which correctly models thermal coupling and is
compatible with the selfheating circuit model described in Chapter One.
Once a valid circuit model for thermal coupling has been developed, it can
be used with the multipleemitter thermal impedance model to perform both steady
state and dynamic electrothermal simulations of multipleemitter BJT/HBT's. The
multipleemitter thermal impedance model expresses the selfheating of an entire
device as the sum of the thermal actions and interactions of the individual emitter
fingers. The thermal model structure requires that a single multipleemitter device be
represented by multiple compact device models. While this configuration allows for
the examination of the EOT of each finger in a device, for devices with a large
number of emitter fingers, the overall electrothermal network can become complex
enough to make moderate to largescale circuit simulations impractical. To make the
multipleemitter electrothermal model more suitable for circuit simulation, its
complexity can be reduced by representing the overall thermal response of the device
by a lumped thermal impedance. The lumped thermal impedance is generated by
applying the measurement approach developed by Zweidinger et al. to the simulation
of the complete electrothermal model [Zwe96]. The thermal impedance extraction
technique is briefly reviewed in this chapter. The lumped model generation
procedure is then described and the results are compared to the complete
electrothermal model.
3.2 A Circuit Model for Thermal Coupling
The EOT of any device in a system of n thermally coupled devices (e.g. a
multipleemitter bipolar transistor with n emitter fingers) can be expressed as
TDEV1(t) = [ATI(t) + AT2(t) + + ATin(t)] +Tamb
TDEV2(t) = [AT21(t) + AT2(t) + + AT2n(t)] +Tamb
TDEVn(t) = [ATnl(t) + ATn2(t) + + AT(t)] + Tamb (3.1)
where ATj(t) = 1 [Zsj P(s)] and ATji(t) = 1 [Zcji Pi(s)]. The impedance Zsj
is the self impedance of device j, and Zcji represents the coupling impedance
between device j and device i. (In general, it is not necessary for Zcji to equal Zcij .)
The modifications described in Chapter One allow circuit simulators to model self
heating; therefore, the EOT of each device in a simulation is calculated by
TDEVj(t) = ATj(t) + Tamb (3.2)
and is independent of its neighbors. The obvious way to expand this technique to
account for interdevice thermal coupling would be to simply tie together the
temperature nodes of individual devices using coupling impedances; this approach
was used by Baureis and Moinian et al. [Bau94, Moi94]. Figure 3.1 shows an
example of such a thermal coupling network for two devices, where
ZC = ZC12 = ZC21. Unfortunately, simple analysis of the circuit in Figure 3.1
shows that it does not correctly model the expression in (3.1). For example, analyzing
TDEV1(t)
? P2(t)
Tamb Tamb
A thermal coupling circuit model for two devices. The temperature
nodes of the two thermally coupled devices are connected using a
thermal coupling impedance.
Figure 3.1
TDEV2(t)
the circuit in the steadystate limit gives the following expression for the EOT of
device 1
Rs I(R + RS2) RslRs2T
TDEV P,+P + Ta m. (3.3)
TDEV (Rc + Rsi + RS2) (Rc + RsI + RS) 2 amb
A similar expression can be derived for the EOT of device 2. The problem with this
network formulation is that when individual temperature nodes are connected
through an impedance path, the entire network becomes distributed among the
coupled devices. The self impedances and coupling impedances, as derived, are not
defined to be distributed elements. In a more simplistic view, the network in
Figure 3.1 does not properly constrain the paths of the respective device power
currents. The powercurrent of a given device is divided between its own self
impedance and the rest of the network. The portion of that device's power flowing
through its neighbor's self impedance has no physical meaning. As a result, the
voltages generated at the temperature nodes do not correspond to the correct device
temperatures.
To develop a correct circuit representation of (3.1) and avoid the
shortcomings of the aforementioned coupling technique, control sources can be
utilized in a thermal coupling network group composed of two subnetworks. Each
device in a group of n thermally coupled devices has its own network group.
Figure 3.2 demonstrates how a thermal coupling network group works. Subnetwork
A attaches directly to the temperature node of device 1. The currentcontrolled
current source (F1) in subnetwork B has unity gain and is controlled by the current
UJ)
TDEV(t)
E12(t)
E13(t)
subnetwork A
Eln(t)
subnetwork B
A new circuit representation of thermal coupling which is compatible
with the selfheating circuit model. Subnetwork A is attached to the
temperature node of a device and represents the total temperature rise
in that device. Subnetwork B is used to calculate the thermal coupling
between devices. The voltagecontrolled voltage sources (E]j)
represent the individual portions of the temperature rise in device 1 due
to the other devices in the circuit. The currentcontrolled current
source (F,) models the power dissipation in device 1.
Fl(t).
Figure 3.2
flowing through the voltage source Vpl in subnetwork A. In this example, Vpl is
also used to set the reference ambient temperature. The voltage drop across each
coupling impedance (Zcil) in subnetwork B corresponds to the portion of the
temperature rise in each device i due to the power dissipation of device 1. The
voltagecontrolled voltage sources in subnetwork A each have unity gain and are
used to couple the voltage drops from each subnetwork B of the other devices, back
to device 1. For example, the value of the voltage source E12 is equivalently
EI2AT12(t), where ZC12 is part of subnetwork B of device 2. Therefore, the
voltage generated at the terminal of subnetwork A corresponds to the EOT of device
1, and is given by the following expression
TDEVI(t) = ATI(t) +ATI2(t) + + ATn(t) +Tamb. (3.4)
Similar expressions can be obtained for the EOT's of the other (n 1) devices in the
circuit since they each have similar thermal networks.
The thermal coupling model is demonstrated by simulating a fivefinger
HBT using a version of SPICE 2G.6 modified to model selfheating [Zwe97]. The
device characteristics are simulated with and without the thermal coupling between
emitter fingers. Figure 3.3 shows the results of the electrothermal simulations. When
accounting for the thermal coupling, the current collapse phenomenon commonly
observed in HBT's can be simulated [Liu93, Sei93, Liu95b]. Figure 3.3b illustrates
how the outer fingers shut down as the middle finger begins to carry all of the current.
The importance of modeling the thermal coupling is established by the fact that the
collapse phenomenon is not reproduced when the simulations only account for self
60
50
E
u 40
t 30
U
2 20
U
CollectorEmitter Voltage, VCE (V)
(a)
40
30
E
u
r
b 20
u
10
U
Figure 3.3
4 6
CollectorEmitter Voltage, VCE (V)
Simulated current characteristics of a fivefinger HBT with
AE = 20 x 2 tm2 for each emitter finger: a) The collector current as a
function of collectoremitter voltage for fixed base currents of 1.0, 2.0
and 3.0 mA; b) the collector current distribution in the device with full
thermal coupling for Ig = 3.0 mA.
  


Full Thermal Coupling
. SelfHeating Only
l ,I ,l iIl
I I I
heating. Multipleemitter devices provide just one application for the thermal
coupling model. It can be used on a larger scale for simulating thermal interactions
within circuits, and it can be used on a smaller scale. By dividing a single device (or
each finger of a device) into multiple subcells, the thermal coupling model could be
used to simulate the temperature distribution within a device and phenomena such as
current constriction [Koe94].
3.3 A Lumped Electrothermal Model for MultipleEmitter BJT/HBT's
Used together with a compact device model of either a BJT or HBT, the
multipleemitter thermal impedance model and the thermal coupling network form a
complete electrothermal model suitable for DC, AC and transient device/circuit
simulation. This type of electrothermal model is generally more efficient for circuit
simulation than either finite difference or finite element techniques; however, it can
be quite complex for devices with a large number of fingers and/or fingers with a
large number of subcells. In such a case, simulating moderate to largesize circuits
could become impractical. The complexity of the electrothermal device model can be
reduced by using a lumped modeling methodology. The measurement technique
described by Zweidinger et al., referred to in this work as basecurrent thermometry,
can extract the thermal impedance of a bipolar transistor using the temperature
dependence of the base current [Zwe96]. By applying this extraction technique to the
simulation of the complete electrothermal device model, a more compact lumped
electrothermal can be produced. The lumped model implicitly contains all the details
of the thermal actions and interactions described by the complete electrothermal
model, but with less complexity.
To present a clear discussion of the lumped electrothermal model
generation methodology, a few definitions and conventions will be established. Due
to the thermal interactions between fingers in a multipleemitter device a lateral
temperature gradient will exist across the device. Therefore, the current distribution
among the fingers may not be uniform since the hotter fingers will carry a larger
amount of current. As power dissipation increases, the lateral temperature gradient
also increases and eventually the device will become unstable and enter either
thermal runaway (BJT's) or current collapse (HBT's). Prior to the onset of thermal
instability, the lateral thermal gradient is small and the current distribution among
the fingers is approximately uniform. When the device reaches the point of thermal
instability, the fingers no longer operate under similar bias conditions and the current
no longer divides evenly among the fingers. Therefore, before a device becomes
thermally unstable, it is defined to be in the uniform operating regime; and, once the
device becomes unstable, it is defined to be in the nonuniform operating regime.
In the uniform operating regime, the EOT of the device varies linearly
with the power and the complete electrothermal model can be represented by a single
lumped device model and lumped thermal impedance, ZTHL. The circuit
representation for the uniform lumped model is shown in Figure 3.4a; the emitter
area of the lumped device model is equal to the total emitter area of the multiple
emitter device. As a device becomes thermally unstable the cooler fingers begin to
turn off, leaving the hottest finger to conduct all of the current; the temperature
Tamb
Tamb
Circuit representations of the lumped multipleemitter BJT/HBT
electrothermal model: a) For the uniform operating regime; b) for the
nonuniform operating regime.
Figure 3.4
power relation becomes nonlinear and the uniform lumped model will not accurately
model the device characteristics. To model this shutdown mechanism, the
nonuniform lumped model, which is shown in Figure 3.4b, uses two lumped device
models and four lumped thermal impedances to represent the entire device. Device
QIF is used to represent the hottest emitter finger. In a device with an odd number of
fingers, the hottest finger will be the middle finger. If a device has an even number
of emitter fingers, due to process variation, the hottest finger will be one of the inner
most fingers. For consistency, in either case the hottest finger will be referred to as
the middle finger. The other device model, QoF, represents the remaining outer
emitter fingers. The emitter area of QIF is equal to that of a single emitter finger and
the emitter area of QOF is equivalent to the sum of the emitter areas of the outer
fingers. The lumped thermal impedances ZSg and Zso model the self impedances of
the middle finger and the outer fingers, respectively. In the case of Zso, the
impedance represents the effective temperature rise in the lumped outer fingers due
only to their power dissipation. The lumped coupling impedance Zclo models the
temperature rise in the middle finger due to the power dissipation in the lumped outer
fingers. The reciprocal coupling impedance Zco1, corresponds to the effective
temperature rise in the lumped outer fingers due to the power generation of the
middle finger.
Thermally triggered instability in bipolar devices can lead to circuit
failure and even catastrophic device failure. Typically, this region of operation is
avoided in circuit design. Therefore, in most cases, the uniform lumped model should
be appropriate for most applications. However, if the effects of thermal instability on
device/circuit operation need to be investigated the nonuniform model should be
used.
3.3.1 A Review of BaseCurrent Thermometry
Basecurrent thermometry uses the base current as a thermometer to
extract the thermal impedance of a bipolar transistor [Zwe96]. The technique was
developed for measurementbased extraction but can be applied to the simulation of
compact device models as long as the models' temperature dependence are
physically valid.
The first step of the procedure is to determine the dependence of the base
current on temperature. The response of the base current to changes in temperature
is represented by the fractional temperature coefficient, defined as
TCF(I) I (3.5)
By biasing a device in the commonemitter configuration (avoiding impact
ionization), and separately varying the collector voltage and the ambient
temperature, the thermal resistance of the device can be extracted Since the base
collector conductance is typically negligible, any changes in the base current during
the measurements are due solely to the change in operating temperature. Therefore,
once the selfheating effects are accounted for, the fractional temperature coefficient
can be determined from the measured base current variations.
The second step of the procedure is to extract the transient thermal
impedance. The collector and base currents of the device are monitored for a step in
the collector voltage. The transient change in temperature can be expressed as
IB(t) IB(0)
AT(t) = (3.6)
IBTCF(IB)
where Ig is the median value of the base current for the transient. The temperature
change is then normalized by the magnitude of the power step, giving the following
equation for the thermal impedance
ZTH(t) AT(t) (3.7)
AP
3.3.2 Generation of the Lumped Electrothermal Model
The first step in the lumped model generation is to extract the temperature
coefficient of the base current by performing DC SPICE simulations at different
ambient temperatures. The .TEMP control card is used to set the ambient
temperature; temperature steps between 4 and 10 degrees are sufficient, where a
geometric mean can be used to average TCF(IB) over temperature to correct for
nonlinearities. The base voltage should be selected for the desired operating point
and for each temperature setting, the collector voltage should be swept over a range
in the forward active region. The range of collector voltages should be large enough
to produce a linear increase in base current. Examples of the resulting base current
characteristics are shown in Figure 3.5. The base and collector current values should

Full Text 
PAGE 1
PHYSICSBASED THERMAL IMPEDANCE MODELS FOR THE SIMULATION OF SELFHEATING IN SEMICONDUCTOR DEVICES AND CIRCUITS By JONATHAN SCOTT BRODSKY A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 1997
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This work is dedicated to my parents, Lawrence and Jeraldine, my brother Matthew and sister Alexandra.
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ACKNOWLEDGEMENTS First, I wish to express my deepest gratitude to my advisor Dr. Robert M. Fox. His constant support and patient guidance provided a clear path for my research. It is both a pleasure and a privilege to have worked with Dr. Fox. I thank Drs. Mark E. Law and Jerry G. Fossum for extending their expertise and help to my unending questions. I would also like to thank Drs. William R. Eisenstadt, John G. Harris and ChenChi Hsu for their willingness to serve on my supervisory committee. I am also very grateful to Mary Turner for all of her help throughout my graduate career. I would like to acknowledge and thank the Semiconductor Research Corporation (SRC) for the financial support that made this research possible. I am also grateful to Dr. Surya Veeraraghavan for his guidance and friendship during my internship at Motorola. I would like to thank the "TCAD elders", and now my friends, Keith Green, Dongwook Suh, PingChin Yeh, Haeseok Cho, ChihChuan Lin, MingChang Liang and Scott Miller, for helping me get comfortable in my new surroundings and setting the standard of excellence. I am also grateful to my good friends/workmates/"happy hour buddies" Srinath Krishnan, Samir Chaudhry, David Zweidinger, Omer Dokumaci, MingYeh Chuang, Dukhyun Chang, Susan Earles, Hernan Rueda, Glenn Workman and Meng111
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Hsueh Chiang, for all of the enlightening discussions, the Friday lunch tradition and the weekend adventures. There is a very special group of individuals who have my admiration and love for the friendships they have given me. I would like to thank my best friends Douglas Weiser, Martin Weiss, Stephen Cea, Edward Cometz and Peter Lynch. I can not completely express the role my family has played in my life and in the completion of this dissertation. For simple words seem to diminish their unconditional and unending love and support. I owe everything I have, everything I have done and everything I am, to my family. I give my deepest love to my parents, Jeraldine and Lawrence Brodsky, my brother Matthew and my sister Alexandra. Finally, I am grateful to all of the wonderful friends that I met in Gainesville for making this period of my life truly enjoyable. IV
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TABLE OF CONTENTS ACKNOWLEDGEMENTS iii ABSTRACT viii 1 INTRODUCTION 1 1 . 1 SelfHeating Effects in Semiconductor Devices 1 1.1.1 Bipolar Transistors 3 1.1.2 FieldEffect Transistors 6 1.2 SelfHeating Effects in Semiconductor Circuits 8 1.2.1 SmallSignal Circuit Performance 8 1 .2.2 LargeSignal Circuit Performance 11 1 .3 SelfHeating Effects in Parameter Extraction 12 1.4 The Simulation of SelfHeating Effects 13 1.5 Thermal Equivalent Circuits 16 1.6 The Need for PhysicsBased Thermal Impedance Models 20 1 .7 Organization 25 2 A THREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR JUNCTIONISOLATED BIPOLAR TRANSISTORS 27 2. 1 Introduction 27 2.2 Derivation of the SingleEmitter BJT/HBT Thermal Impedance Model. . . 28 2.2. 1 Modification for Finite Wafer Thickness 39 2.2.2 Effects of Interconnect Metallization on the Thermal Impedance ... 43 2.2.3 A Model for the Thermal Impedance of the Emitter Interconnect ... 49 2.2.4 Effects of Isolation Structures on the Thermal Impedance 52 2.3 Verification of the SingleEmitter Thermal Impedance Model 61 2.4 Derivation of the MultipleEmitter BJT/HBT Thermal Impedance Model . 66 2.5 Verification of the MultipleEmitter Thermal Impedance Model 72 2.6 Summary 76 3 A CIRCUIT MODEL FOR THERMAL COUPLING AND A LUMPED ELECTROTHERMAL MODEL FOR BULK MULTIPLEEMITTER BIPOLAR TRANSISTORS 77 3.1 Introduction 77 3.2 A Circuit Model for Thermal Coupling 80
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3.3 A Lumped Electrothermal Model for MultipleEmitter BJT/HBT's 86 3.3.1 A Review of BaseCurrent Thermometry 90 3.3.2 Generation of the Lumped Electrothermal Model 91 3.4 Verification of the Lumped Electrothermal Model 96 3.5 Summary 101 A THREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR VERTICAL BIPOLAR TRANSISTORS FABRICATED WITH FULL DIELECTRIC ISOLATION 103 4. 1 Introduction 103 4.2 Derivation of the DIBJT Thermal Impedance Model 106 4.2.1 Derivation of the BuriedOxide HeatTransfer Coefficient 1 16 4.2.2 Derivation of the Trench HeatTransfer Coefficient 120 4.2.3 Effects of Interconnect Metallization on the Thermal Impedance . . 126 4.2.4 A Model for the Thermal Impedance of the Emitter Interconnect . . 129 4.3 Verification of the DIBJT Thermal Impedance Model 132 4.4 Derivation of a Compact DIBJT Thermal Resistance Model 134 4.5 Verification of the DIBJT Thermal Resistance Model 146 4.6 Summary 149 A THREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR BULK METALOXIDESEMICONDUCTOR FIELDEFFECT TRANSISTORS ..150 5. 1 Introduction 1 50 5.2 Derivation of the Bulk MOSFET Thermal Impedance Model 153 5.2.1 The Linear Source Thermal Impedance 161 5.2.2 The Saturated Source Thermal Impedance 164 5.2.3 Effects of the Device Interconnects on the Thermal Impedance ... 165 5.2.4 Effects of Isolation Structures on the Thermal Impedance 171 5.3 Verification of the Bulk MOSFET Thermal Impedance Model 176 5.4 Summary 182 A QUASITHREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR SILICONONINSULATOR METALOXIDESEMICONDUCTOR FIELDEFFECT TRANSISTORS 184 6. 1 Introduction 1 84 6.2 Derivation of the SOI MOSFET Thermal Resistance Model 187 6.3 Verification of the SOI MOSFET Thermal Resistance Model 202 6.4 Derivation of the SOI MOSFET Thermal Impedance Model 204 6.5 Verification of the SOI MOSFET Thermal Impedance Model 212 6.6 Summary 216 THE THERMAL IMPEDANCE PREPROCESSOR: TIPP 219 VI
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7. 1 Introduction 219 7.2 A Description of TIPP 220 7.3 Generation of Thermal Equivalent Circuits 225 7.3.1 Approximation of the Thermal Equivalent Poles/Time Constants. . 226 7.3.2 Calculation of the Thermal Equivalent Components 230 7.4 The Interface Between TIPP and Circuit Simulators 232 7.5 Summary 234 8 CONCLUSIONS AND RECOMMENDATIONS FOR FUTURE WORK ... 238 8. 1 Conclusions 238 8.2 Recommendations for Future Work 240 8.2.1 The Temperature Dependence of the Thermal Conductivity 240 8.2.2 Models for Thermal Effects Due to Advanced Isolation 242 8.2.3 A Model for Thermal Coupling in SOI MOSFET Circuits 243 REFERENCES 247 BIOGRAPHICAL SKETCH 257 vn
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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy PHYSICSBASED THERMAL IMPEDANCE MODELS FOR THE SIMULATION OF SELFHEATING IN SEMICONDUCTOR DEVICES AND CIRCUITS By Jonathan Scott Brodsky August 1997 Chairman: Robert M. Fox Major Department: Electrical and Computer Engineering Inherent in the operation of semiconductor devices is selfheating, an increase in operating temperature due to a device's own power dissipation. The magnitude of the selfheating effect can be quantified by the value of the thermal impedance, which describes the dynamic response of the device temperature to variations in device power. The thermal impedance is determined primarily by material properties and device structure. The implication of the selfheating effect is that the change in temperature can alter the operating characteristics of a device, which in turn, can affect circuit performance. The primary focus of this dissertation is the development of physicsbased models for the thermal impedances of semiconductor devices. Models for the thermal impedances of bipolar and fieldeffect transistors, on both bulk and silicononVlll
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insulator (SOI) substrates, are presented. All of the thermal impedance models were derived from the timedependent heat conduction equation, resulting in compact analytic expressions for the thermal impedances. The physical nature of the thermal impedance models allows them to scale with the device structure and material properties, and they successfully reproduce results from both measurements and threedimensional finiteelement simulations. A circuit model for thermal coupling between transistors in a common substrate is also presented. The coupling model was used in conjunction with the bulk bipolar thermal impedance model to extract a lumped electrothermal model for multipleemitter bipolar transistors. The secondary objective of this work is the provision of an approach for incorporating these models into circuit simulators. It has been shown that the thermal impedance models can be represented by thermal equivalent circuits made up of resistors and capacitors, making them suitable for efficient circuit simulation. The computer program TIPP (Thermal Impedance PreProcessor) is introduced. TIPP was developed to provide circuit simulators with convenient algorithms for generating thermal equivalent circuits. TIPP can calculate the component values for thermal equivalent circuits from either physical models or measured data, and is easily modified to interface with different circuit simulators. IX
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CHAPTER 1 INTRODUCTION 1.1 SelfHeating Effects in Semiconductor Devices The physical properties of the materials used to fabricate semiconductor transistors depend on temperature. Therefore, the operating characteristics of a transistor (e.g. electrical currents and potentials), which are determined by the material properties, are also temperature dependent. The temperature at which a transistor operates is determined by the temperature of the surrounding environment (referred to as the "local ambient temperature") and the power dissipated in the device (referred to as the "selfheating effect"). Therefore, the timedependent temperature of a transistor can be expressed as t T(0 = T amb + JP(t')h TH (tt')dt\ (1.1) o where h TH is the thermal impulse response and P is the instantaneous power. The second term on the righthand side of (1.1) represents the temperature rise in the device AT(t) = PÂ®h TH , (1.2) where Â® is the convolution operator. The temperature rise can also be expressed in
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the frequency domain as AT(t) =r 1 [Z TH (s)P(s)], (1.3) where Â£" ] represents the inverse Laplace transform and Z TH (s) is the thermal impedance. The thermal impedance of a transistor describes the dynamic response of the device temperature to variations in device power, and is determined primarily by the material properties and the structure of the device. The transient thermal impedance can be defined as Z TH (t) =Â£"' th' S ' (1.4) which represents the normalized thermal step response. Since the power dissipation in (1.1) is determined by the operating characteristics of a transistor, it depends on temperature such that P = P(T) = I dev (T)V dev (T), (1.5) where I dev (T) and V dev (T) represent general currents and potentials within a given device, respectively. Consequently, there is feedback between the thermal and electrical operation of the device. Whereas the transistor temperature is usually assumed to be constant, the electrothermal coupling implied by ( 1 . 1 ) and ( 1 .5) shows that the temperature actually varies with the device operation. Thus, to fully characterize the operation of semiconductor transistors, both the electrical and thermal behavior should be determined.
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1.1.1 Bipolar Transistors In the forwardactive mode, the operating characteristics of bipolar junction and heterojunction transistors (BJT's and HBT's) are controlled by the injection and diffusion of minority carriers in the base region. For an npn transistor, electrons are injected across the forwardbiased base/emitter junction, causing an exponential increase in the minority carriers in the base. The electrons diffuse across the base and are swept into the collector by the reversedbiased base/collector junction. For a fixed base/emitter voltage, assuming negligible recombination in the quasineutral base, the collector current can be expressed as I c (T)nf(T)ex P Ppj^], (1.6) where n, is the intrinsic carrier concentration, q is the electron charge, k is Boltzman's constant and T is temperature. The overall temperature dependence of (1.6) is dominated by the relation between the intrinsic carrier concentration and temperature, given by n?(T) = N c N v exp^J, (1.7) where E is the semiconductor bandgap energy and N c and N v are the effective density of states in the conduction and valence bands, respectively. The junction voltage is always less than the bandgap and therefore, an increase in temperature causes an exponential increase of minority carriers in the base, resulting in an increase in collector current. Since the collector current is a significant component
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of the power dissipation in a BJT, selfheating results in a regenerative feedback between the collector current and the temperature of the device. This positive feedback can lead to the destructive phenomenon of thermal runaway in BJT's [Shu90]. For fixed base current, the collector current can be expressed as I C (T) = P(T)I B , (1.8) where (3(T) is the commonemitter current gain. For moderate injection levels, the current gain can be approximated by the ratio of the electrons injected into the base to the holes backinjected from the base to the emitter. This ratio, and hence P(T), are typically high since the emitter usually has a higher doping level than the base. Due to heavydoping effects in the emitter, the emitter bandgap is typically less than that in the base so that p(T) ~N7B exp M' (l9) where AE g is the bandgap difference between the emitter and base, and N DE and N AB are the doping concentrations in the emitter and base, respectively. As shown by (1.9), the current gain is greater at higher temperatures; consequently, the collector current is, again, an increasing function of temperature. The rate of increase with temperature in this case, however, is not as significant as that for a device biased with a fixed base voltage. Therefore, the selfheating effect is not as substantial in BJT's driven by a fixed base current.
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HBT's are bipolar devices that use bandgap engineering in either the emitter or base region to improve the current gain over homojunction BJT's. The resulting bandgap in the emitter is wider than that in the base, so that the potential barrier induced by the bandgap discontinuity effectively impedes the injection of carriers from the base to the emitter. When biased with a fixed base voltage, the temperature dependence of an HBT is similar to that of a standard BJT. However, when an HBT is driven with a fixed base current, the temperature dependence of the collector current is quite different than that of a BJT. While the collector current in this case can still be determined from ( 1 .8), the commonemitter current gain is now expressed as p p Ut 8 I< iio > As a result of the bandgap being wider in the emitter than in the base, the sign of the exponential argument is now positive. Therefore, as opposed to a standard BJT, the current gain and the collector current decrease with increasing temperature. As a result, selfheating in HBT's can lead to the noncatastrophic failure mechanism known as current collapse [Sei93]. To reduce the effects of parasitic resistances and currentcrowding, large bipolar devices are commonly fabricated using multiple devices connected in parallel [Shu90]. Multipleemitter devices, both BJT's and HBT's, are capable of operating at high frequencies under high power densities [Win67, Mar93, Liu95b]. However, multipleemitter devices suffer from more complex selfheating effects due to the thermal interactions among neighboring devices. The thermal coupling leads to
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lateral temperature gradients across the device, resulting in the inner emitters operating at higher temperatures. Due to the positive feedback between junction temperature and junction current, the inner devices carry more current than those at the outer extremes. As the current density in the inner emitters increases, the selfheating effect in these devices accelerates. The premature activation of thermal runaway in BJT's and current collapse in HBT's is attributed to this thermal instability inherent in multipleemitter devices [Win67, Liu93, Kag94, Lio94, Lio96]. 1.1.2 FieldEffect Transistors For MetalOxideSemiconductor FieldEffect Transistors (MOSFET's) operating in strong inversion, the current characteristics are determined by the drift current of carriers in the inverted channel region. For small drain voltages, a MOSFET operates in the linear region where the carrier velocity depends on the longitudinal electric field in the channel. In the linear region, the drain current can be approximated as I D (T)^(T)(v GS V t (T)^]v DS , (1.11) where i(T) is the carrier mobility, V t (T) is the threshold voltage, and V GS and V DS are the applied voltages between the gate and source and drain and source, respectively. At higher drain voltages, the electric field at the drain end of the channel is large enough to cause the carrier velocity to saturate. In the saturation
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region, the drain current can be expressed as I D (T)ocQ c (V GS ,V DS ,^(T))v sat (T), (1.12) where Q c is the channel charge and v sat (T) is the saturated carrier velocity. The overall temperature dependences of (1.1 1) and (1.12) are dominated by the sensitivity of the carrier mobility to changes in temperature. Due to increased lattice scattering at higher temperatures, mobility decreases as temperature increases. The reduction in mobility leads to a decrease in drain current, which implies that the drain current of a MOSFET is a decreasing function of temperature. At high power dissipation levels, the selfheating effect can cause the drain current to drop below the ambient temperature value. In such cases, the output conductance becomes negative, and the device exhibits a negative dynamic resistance (NDR) [Sha83]. MOSFET's fabricated on silicononinsulator (SOI) substrates have temperature dependences that are similar to those of their bulk counterparts, though the effects of selfheating can be enhanced due to the low thermal conductivity of the insulating layers. For nonfully depleted (NFD) SOI MOSFET's, however, floatingbody effects further complicate the thermal effects [Wor97]. Impactionizationinduced floatingbody effects are known to cause the kink, or increase in drain current, in NFD SOI MOSFET's. The kink is affected by selfheating in two ways. First, at elevated temperatures, the onset of the impactionization is retarded. Second, an increase in recombination in the quasineutral body reduces the thresholdvoltage shift caused by the impactionization. Therefore, in addition to a reduction in drain current due to mobility effects, selfheating also reduces the
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current in NFD SOI MOSFET's through temperaturedependent floatingbody effects. 1.2 SelfHeating Effects in Semiconductor Circuits Since the operating characteristics of transistors are affected by temperature, the integrated circuits that depend on these transistors will also be affected by changes in temperature. In modern digital circuits, the high switching speeds of the transistors, the relatively slow time constants associated with the temperature response and the low static power dissipation, all help reduce the instantaneous temperature rise. Consequently, selfheating effects are typically negligible in digital circuits. On the other hand, analog circuit applications commonly have significant power dissipation and can operate at frequencies which are comparable to the thermal timeconstants. Therefore, analog circuits are generally more prone to selfheating effects. 1.2.1 SmallSignal Circuit Performance The effect of selfheating on smallsignal BJT characteristics was derived by Mueller and investigated in bipolar circuits by Fox et al. [Mue64, Fox93b]. The twoport smallsignal admittance parameters, in the presence of selfheating, were shown to be ymnE + D m Z TH I m I n ,, ,ox ^ran Â— i pv v p ' * ' 1 ~ u m^lH r
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where y mnE are the admittance parameters neglecting selfheating, and D m represents the variation of the current I m with temperature. The denominator of (1.13) establishes the sensitivity of the admittance parameters to power, and has a significant impact as D m Z TH P approaches unity. The effect of the denominator generally becomes important only at high power dissipation. However, as the thermal impedance increases (i.e. due to device scaling), the power level that defines the threshold for selfheating effects will decrease. The second term in the numerator of (1.13) shows that the effect of selfheating on the admittance parameters is also proportional to the operating currents. For y n and y 21 the selfheating term in the numerator is small so that y,, =Yhe and y 21 =y2iEHowever, the effect of selfheating can be substantial in the numerators of y p and y 22 , even at moderate current levels. The thermal effects on these parameters can result in a coupling between the collector output admittance and the impedance of the basedriving source. Also, as shown in Figure 1.1, there can be a significant reduction in the voltage gain of BJT amplifiers. The smallsignal performance of analog MOSFET circuits can also be affected by selfheating. For moderate power levels, the thermal effects are similar to those in bipolar circuits. However, as mentioned previously, the drain current of a MOSFET decreases with increasing temperature, and significant selfheating can induce NDR. The effect of a negative output conductance can be investigated by examining the voltage gain of a MOSFET amplifier. As shown by Fox and Brodsky [Fox93a], if the devices in the amplifier enter a region of negative output conductance, the gain of the amplifier changes polarity. For an inverting amplifier,
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10 300 > g a c
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11 selfheating effects can therefore cause the gain to become noninverting, resulting in hysteresis in the amplifier's output characteristics. 1.2.2 LargeSignal Circuit Performance The effects of selfheating on the largesignal operation of analog bipolar circuits was investigated by Fox et al. [Fox93b]. The types of circuits that are sensitive to thermal effects are typically those that depend on the precise control of BJT characteristics. For example, the mismatch in the reference and output currents of a current mirror can be increased due to selfheatinginduced differences in the operating conditions of the transistors. Translinear circuits and bandgap voltage references can also be affected by selfheating due to their strong dependence on the thermal voltage. Thus, neglecting selfheating can result in significant discrepancies between the ideal and actual operation of these types of circuits. The largesignal transient operation of analog circuits is also affected by selfheating. The long time constants of the thermal characteristics can effectively slow down the electrical response of a circuit. Fox et al. showed that the fivepercent settling time of a Gilbert multiplier increased by over an order of magnitude due to selfheating [Fox93b]. While the errors caused by selfheating can be reduced by careful circuit design, they can not be completely eliminated.
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12 1.3 SelfHeating Effects in Parameter Extraction The extractions necessary to determine the behavioral characteristics of a semiconductor transistor are often performed at bias levels that cause moderateto highpower dissipation. Typically, the parameters that are extracted are assumed to correspond to the ambient temperature at which the measurements are carried out. However, at significant power levels, selfheating will cause a temperature rise in the device. Neglecting the temperature rise that can occur during the measurements can lead to erroneous results [Zwe97]. For example, the Early voltage, V A , of a BJT is commonly extracted from the slope of the I C V CE characteristics in the linear region of operation. If selfheating is significant, the slope of the output curves depends on the source that is driving the base [Fox93b]. Therefore, the exact meaning of the value extracted for V A would be ambiguous unless the thermal effects were taken into account. Various methods have been proposed for removing the effects of selfheating from parameter extraction. One approach augments a standard extraction routine with measurements designed to determine the thermal characteristics of the device. The full set of parameters can then be input to a global optimization routine to generate electricalonly parameters that are independent of selfheating [Zwe97]. Other techniques attempt to directly remove the effects of selfheating from the parameter extraction measurements by making the temperature rise in the given device negligible. The temperature rise can be minimized by performing the extractions in lowpower regions, or by using complex highspeed measurements [Tu94, Jen95]. Since the device is not allowed to heat, the resulting device parameter
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13 set would be approximately devoid of selfheating effects, and would essentially correspond to the given device operating under isothermal conditions. Consequently, the resulting electrical parameters would only pertain to device operation for lowpower or highspeed circuit applications, and would not convey the proper device characteristics for applications that experience substantial selfheating effects. Thus, for a set of electricalonly parameters to correctly represent the characteristics of a device, over a wide range of operating conditions and biases, it should be augmented by additional parameters that describe the thermal attributes of the device. 1.4 The Simulation of SelfHeating Effects As shown in the previous sections, the operating characteristics of both individual transistors and circuits depend on temperature. Due to selfheating, the effective operating temperature depends on power dissipation and can therefore vary under different operating conditions. By solving the timedependent heat conduction equation and energy balance equations for electrons and holes, numerical device simulators can model phenomena associated with dynamic selfheating in individual transistors [Lia94]. While this approach is invaluable for examining the detailed physics that govern the operation of semiconductor devices, it is impractical for simulating all but the simplest of circuits. Therefore, to investigate the effects of dynamic selfheating on a broad range of circuits, a more efficient simulation approach is necessary.
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14 The standard version of most circuit simulators such as Berkeley SPICE [Nag75] and HSPICE [Hsp92], treat temperature as a static global parameter. This has two significant implications. All of the semiconductor devices in a simulation operate at the same temperature, and that temperature remains constant throughout the simulation. Due to these constraints, a circuit simulator may not accurately represent the physical operation of a circuit, where spatial and temporal variations of the temperature can cause each device to operate at its own local temperature. To account for the temperature dependence of a circuit's operation, circuit simulators should be capable of independently tracking the dynamic temperature of each device in the circuit. A common approach for creating an electrothermal circuit simulator (ETCS) uses the concept of the thermal impedance and the analogy between electrodynamics and heat flow to account for dynamic temperature variations. This approach allows temperature to be represented as an electrical potential and power as an electrical current [Lee96, Zwe97]; therefore, the local operating temperature of a device can be thought of as simply another "bias" condition. To facilitate the temperature "bias" condition, an external node is added to a given compact device model [McA92, Fos95, Lee96, Zwe97]; such a configuration is shown in Figure 1.2. Attached to this node, internal to the device model, is a controlled current source that represents the instantaneous power dissipation. The parameter set for the device model should be modified to include the correct temperature dependences. When the modified device model is used for a circuit simulation, a thermal impedance (and, in some case, a voltage source to represent the reference ambient temperature) can be
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15 T op (t) P(t) o amb Figure 1.2 A generalized schematic showing a common method for modifying a compact device model to include temperature as a variable. The dashed box outlines the new model with the added temperature node; DEVICE represents the original electricalonly model.
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16 attached to the new external node. Therefore, the voltage generated at this additional node represents the local temperature of the device. The electricalonly device model is first solved at the ambient temperature; this solution results in an initial guess for the device power dissipation. This power is then used to calculate the temperature rise in the device. Once the approximate local operating temperature is calculated, it is used to update the temperaturedependent model parameters, which are used to recalculate the electrical bias potentials and currents of the device model. This procedure is repeated until selfconsistent solutions for the temperature and electrical biases are reached. Thus, an effective operating temperature can be independently calculated for each device in a simulation, and that temperature can now vary with the operating point. 1.5 Thermal Equivalent Circuits The data that quantify the thermal impedance of a transistor are typically in the form of discrete data points for the temperature rise, normalized to a unitstep increase in power dissipation, versus time or frequency. In such a format, the thermal impedance data are not readily accessible by an ETCS. While data in a tabular format can be used without much complexity for DC and AC simulations, an inefficient convolution computation would be required to use the data for transient simulations. Therefore, a representation for the thermal impedance is needed that both accurately models the physical data and can be easily incorporated into an ETCS for efficient DC, AC and transient simulations.
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17 In an ETCS, when a current representing the power dissipation in a transistor is applied to the thermal impedance, Z TH , the resulting voltage represents the temperature rise in that transistor. By invoking the analogy between electrodynamics and heat flow, the thermal impedance can be represented as an electrical impedance. Common representations for the electrical impedance circuits are shown in Figure 1.3. The resistances and capacitances that comprise the impedance effectively represent the lumped threedimensional thermal resistance and heat capacity of the semiconductor device structure. Therefore, the overall electrical network can be referred to as a thermal equivalent circuit. The values for the individual elements of a thermal equivalent circuit can easily be determined by numerically fitting the circuit to existing thermal impedance data. Thermal equivalent circuits are directly applicable for DC and AC electrothermal simulations since, in such cases, the voltage drop across the network is simply equal to the product of the current and the network resistance or impedance. In addition, such networks inherently provide an efficient method for effecting the necessary transient convolution. As will be shown in the subsequent chapters of this dissertation, the fundamental nature of heat flow is that of a distributed system. The dynamic temperature rise in a device due to selfheating can occur over three or more decades of time or frequency. A single time constant associated with a simple exponential function can not represent the distributed behavior of selfheating. Consequently, the network response of the singlepole thermal equivalent circuits which have been proposed in previous works [McA92, Bau93, Lee93, Tu94], will not accurately
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18 r thl r th2 r th3 o Â— VvVt Â— WVÂ— ? Â— VW c thi Cth2 c th3 (a) r thl r th2 r th3 rYAn rAVn r^VWi c thi c th2 (b) c th3 Figure 1.3 Thermal equivalent circuits used to represent a thermal impedance for circuit simulation: a) Cauer network representation; b) Foster network representation.
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19 model the dynamic thermal impedance. Thermal equivalent circuits consisting of cascaded resistor/capacitor stages, as exemplified in Figure 1.3, effectively provide a distributed network response, and therefore allow a more accurate representation of a dynamic thermal impedance [Bro93]. In the work by Szekely and Van Bien [Sze88], the Foster circuit (Figure 1.3b) was shown to be an invalid representation of a discretized thermal network. This point is valid in the context of numerical simulations (e.g. finite difference or finite element) where the transistor structure is modeled by a distributed thermal network. In that case, the nodetonode capacitances of the Foster network do not have physical meaning and the Cauer network would be the proper physical discretization of the given thermal domain. However, in this dissertation, the thermal equivalent circuit is simply a numerical representation of a thermal impedance, and the validity of its format is moot. Yet, for the purpose of representing a lumped thermal impedance in an ETCS, the Foster network form offers an important advantage over the Cauer form: the time constants associated with a given Foster network are independent of any surrounding circuit elements. This characteristic is beneficial when individual thermal equivalent circuits must be connected to model different components of a transistor structure or the thermal interactions between transistors. Therefore, the Foster network form will be assumed for any thermal equivalent circuits within this dissertation.
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20 1.6 The Need for PhysicsBased Thermal Impedance Models In the previous two sections, the concept of the thermal impedance is adopted to model the temperature rise in a transistor as a function of that device's power dissipation. For the purpose of circuit simulation, the thermal impedance can be represented by a network of resistances and capacitances that effectively represent the lumped thermal characteristics of a transistor. To successfully synthesize a thermal equivalent circuit, tangible data for the thermal impedance are necessary. One approach to obtain the thermal impedance of a transistor is to extract it from measurements [Lee95, Zwe96]. While this empirical approach provides accurate temperature information, such measurements are somewhat difficult, for several reasons. To begin with, thermal measurements are very timeconsuming. The extraction procedure is generally divided into two steps, the first of which dominates the total measurement time. This step is required to calibrate the relation between the temperature and the physical characteristic that is being used to monitor the temperature (e.g. the base current and drain current in bipolar and fieldeffect transistors, respectively). The calibration is performed at multiple ambient temperatures at DC and is thus limited by the long time constants associated with steadystate heat flow. To make such thermal measurements requires special measurement equipment such as a thermal wafer chuck or oven to accurately control the temperature of the devices being measured. Finally, the results of any such extraction are limited to the specific device being measured. Thus, the entire procedure would have to be repeated for each transistor structure and transistor type of interest.
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21 Another approach, which avoids the inherent complexities of thermal measurements, is to derive the thermal impedance of a transistor from the physical equations that govern the temperature and heat flow in the device. Physical thermal modeling is desirable because it can give the temperature behavior as a function of the device structure and material properties alone; therefore, the effects of device technology scaling on the thermal impedance can be predicted. The requirements of accurate physical modeling (e.g. multidimensional numerical simulations) tend to conflict with the needs for simplicity and efficiency in circuit simulation. However, a thermal impedance model does not need to be absolutely accurate to provide reasonable results within an ETCS. Therefore, by using certain heuristic assumptions, compact physical models for the thermal impedance, suitable for efficient simulation, can be derived. It is important, though, that the correlation between the accuracy of the thermal impedance models and the accuracy of the simulated electrical characteristics of a semiconductor device in the presence of selfheating be understood. The sensitivity of a given electrical parameter, X, of a semiconductor device to the thermal resistance can be defined as ,Rth_^jh _ax X ' dR s TH = _m _^~_ ( j j 4) TH As an example, since the output current of a device is very important for characterizing performance, (1.14) can be used to determine the sensitivity of the collector and drain currents of BJT's and MOSFET's, respectively. Using (1.1) in the steadystate limit and (1.6) with (1.14), the sensitivity of the collector current of a
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22 BJT is expressed as Â„R TH q(Vgv B E)RTHP ^I j Â— . (115) k(R TH P + T ) 2 where V g is the semiconductor bandgap voltage. A similar expression for the sensitivity of the drain current of a MOSFET can be determined using the current equation given by Fox and Brodsky [Fox93a], which results in SR TH I = oc 'd R TH ' P " Â• T i R TH P To (1.16) where a is typically between 1.5 and 1.8 (assuming that the temperature dependence of the drain current is dominated by the temperature sensitivity of the carrier mobility). The expected level of error in simulated output currents can be approximated by the product of the sensitivity and the anticipated error in the thermal impedance model. Therefore, as shown by ( 1 . 1 5) and ( 1 . 1 6), the relation between the accuracy of the thermal impedance models and the accuracy of the calculated electrical parameters depends on the power dissipation and the sensitivity of the electrical parameters to temperature. Consequently, the level of accuracy of a thermal impedance model is more critical for devices with electrical characteristics that are highly sensitive to temperature (e.g. BJT's as opposed to MOSFET's). At low power dissipation levels, where the temperature rise is small compared to the ambient temperature, the error in the thermal impedance model will not directly correspond to the error in the calculated operating temperature. For a temperature rise of twenty degrees, the sensitivities of the BJT collector current (V BE = 0.8) and
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23 MOSFET drain current are 0.7 and 0. 1 , respectively. In such a case, the error in the electrical characteristics will tend to be lower than the error in the thermal impedance. Whereas at large power dissipation levels, the temperature rise can be much larger than the ambient temperature, and the error in the thermal impedance model will directly correspond to the error in the calculated operating temperature (for a temperature rise of onehundred degrees, the respective BJT and MOSFET current sensitivities are 2 and 0.4); in which case, large errors in the calculated electrical characteristics can result. Figure 1.4 shows an example of BJT characteristics simulated assuming a 20% error in the thermal resistance model; the simulations were performed using the modified version of SPICE created by Lee [Lee96]. The data clearly shows that for larger temperature rises, the error in the calculated current (due to errors in the thermal impedance model) increases. The motivation behind this dissertation is the development of compact thermal impedance models for semiconductor transistors. These models can provide a reasonably accurate representation of the dynamic temperature response within a device; more importantly, since the models depend mainly on the physical structure of a device, they can correctly anticipate the effects of technology scaling on the thermal behavior. Physicsbased thermal impedance models allow an ETCS to predict dynamic selfheating effects in circuits and can also provide more accurate electrical parameter extraction. In addition, when the thermal impedance models are coupled with physicsbased compact device models, the combination provides an efficient tool for studying selfheating in semiconductor transistors.
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24 40 30 c o fc 20 3 U o "o U R TH = 1000 Â°C/W R TH = 800 Â°C/W 12 3 4 CollectorEmitter Voltage, V CE (V) Figure 1.4 Simulated output characteristics of a BJT, assuming that R TH = 1000 Â°C/W, for V BE =0.80, 0.85, 0.90 and 0.95 V. The simulations are repeated assuming a 20% error in the thermal resistance model, so that R TH = 800 Â°C/W.
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25 1.7 Organization Chapter Two presents a physicsbased model for the thermal impedance of bulk junctionisolated bipolar transistors. The model is derived by solving the threedimensional timedependent heat conduction equation in the substrate. The ability of the model to represent bulk BJT/HBT's with either LOCOS or trench isolation is investigated. To account for multipleemitter bipolar transistors, the thermal impedance model is extended to represent multiple heat sources. The accuracy of the model is evaluated using measurements and threedimensional finiteelement simulations. Chapter Three describes a circuit network for modeling thermal interactions between devices located in the same substrate. The network is developed for the specific application of multipleemitter bipolar devices, but is shown to be valid for general crosssubstrate thermal coupling in circuits. A method for improving the simulation efficiency of a multipleemitter BJT/HBT electrothermal model, using a lumped thermal impedance model, is presented. The validity of the lumped modeling approach is supported with comparisons to the full electrothermal model. Chapter Four presents a predictive scalable model for the thermal impedance of BJT's with full dielectric isolation. The model is derived by solving the threedimensional timedependent heat conduction equation in the substrate accounting for the buried oxide and trench isolation. In the limit of steadystate heat conduction, the thermal impedance model is simplified, resulting in a closedform
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26 model of the thermal resistance. The accuracy of both models is evaluated using threedimensional finiteelement simulations and measurements. Chapter Five describes a physicsbased model for the thermal impedance of bulk. MOSFET's. The model is derived by solving the threedimensional timedependent heat conduction equation in the substrate. The effects of the device interconnects and isolation structures, such as LOCOS and trenches, on the thermal impedance are investigated. The accuracy of the model is evaluated using measurements and threedimensional finiteelement simulations. Chapter Six presents a predictive scalable model for the thermal impedance of SOI MOSFET's. The model is initially derived for steadystate heat conduction by coupling separate onedimensional heat conduction analyses in the silicon film and interconnects. The derivation is then carried out for the case of timedependent heat conduction, resulting in a model for the dynamic thermal impedance. The accuracy of both models is evaluated using threedimensional finiteelement simulations and measurements. Chapter Seven describes a computer program developed to facilitate thermal modeling in circuit simulation. The program, referred to as the Thermal Impedance PreProcessor (TIPP), functions as a framework for obtaining the component values of thermal equivalent circuits from the thermal impedance models presented in Chapters Two through Six. Chapter Eight concludes the dissertation with a summary of the accomplishments of this work and suggestions for future modeling efforts.
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CHAPTER 2 A THREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR JUNCTIONISOLATED BIPOLAR TRANSISTORS 2.1 Introduction The models derived in this chapter provide closedform physical solutions for predicting the thermal impedances for singleand multipleemitter bipolar junction (BJT) and heterojunction bipolar (HBT) transistors, based solely on device geometry and material properties. These models can predict both steadystate and dynamic selfheating due to the semiconductor substrate. Previous works in this area provided values for the thermal impedance of BJT's or HBT's, but were either limited by assumptions or relied on nonpredictive measurement techniques. For example, the thermal impedance model derived by Fox and Lee [Fox91a] is limited to singleemitter devices. The analyses in other works only provide models for the steadystate thermal resistance [Lio93, Bau94, Daw94, Lio94, Lio96]. Some authors have used measurement techniques to extract either the steadystate thermal resistance or simple onepole approximations for the thermal impedance [Bau93, Liu93, Daw94, Liu95a, Liu95b]; in either case, the results do not provide a complete picture of selfheating and are not predictive. The thermal analysis by Joy and Schlig [Joy70] serves as the foundation for deriving of thermal impedance model, and the first part of this chapter re27
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28 examines this work to provide a clear background for modifications made to the model later in the chapter. The thermal impedance model developed by Joy and Schlig was derived for singleemitter, junctionisolated BJT's operating in the forwardactive region. A diagram of a typical junctionisolated npn BJT is shown in Figure 2.1. In this chapter, the basic model is modified to account for variations in substrate thickness. The effects of interconnect metallization and different isolation technologies on the thermal impedance, and thus on the performance of the model for advanced device structures, are investigated. The singleemitter thermal impedance model is finally extended to account for BJT/HBT's with multiple emitter fingers. 2.2 Derivation of the SingleEmitter BJT/HBT Thermal Impedance Model For the derivation of the singleemitter bulk BJT/HBT thermal impedance model, the semiconductor substrate is represented by a homogeneous semiinfinite halfspace with an adiabatic top surface (no heat transfer perpendicular to the surface). The back side of the substrate is assumed to be held at a constant temperature, T . Since the substrate material is assumed to be homogeneous, the model most directly applies to junctionisolated transistors. The effects of other types of isolation structures used in bulk technologies, such as recessed LOCOS (local oxidation of silicon) or backfilled trenches, on the thermal response are not taken into account. Figure 2.2 illustrates the simplified device geometry assumed for the model derivation; the diagram focuses on the "electrically active" portion of the device that lies directly beneath the emitter stripe, which has a width W and length
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29 Oxide Collector O JZZ Emitter Z2 e Base O I " " ; TI 2 UZ IT" ZL Oxide 7 n n+ psubstrate Figure 2. 1 Crosssection of a typical junctionisolated bipolar junction transistor (BJT).
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30 (dT/dz) = D H ^ Figure 2.2 The simplified device geometry used to define the solution domain for the bulk, singleemitter BJT/HBT thermal impedance model. The substrate is represented by a semiinfinite halfspace with an adiabatic surface (the dotted lines). The emitter stripe has a width W and length L. The heat source (the rectangular volume) is displaced a distance D below the surface of the device, equivalent to the depth of the base/ collector junction. The heat source has a thickness H which approximates the base/collector spacecharge region (SCR).
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31 L. The imbedded heat source represents the base/collector spacecharge region (SCR), which is further represented by a rectangular volume with a thickness, H . The heat generated in this region is assumed to be due to uniform power dissipation. This assumption is reasonable for devices in the forwardactive region of operation prior to any high current effects, as the current distribution in the intrinsic device will be approximately uniform. The electric field gradient in the base/collector SCR can also be neglected since it does not greatly affect the thermal impedance model. The heat source is displaced beneath the surface of the substrate by a distance D, assumed to be the depth of the base/collector junction. Thus, any encroachment of the base/ collector SCR into the base region is neglected (which is reasonable since the base typically has a higher doping than the collector). Representing the substrate as a semiinfinite medium presumes that the backside and the lateral edges do not influence the thermal response of the device. Neglecting the effects of the back side of the substrate on the thermal response is reasonable since a typical wafer is about 1000 times thicker than the heat source. Neglecting the effects of the lateral boundaries requires that the device be located sufficiently far from the substrate edges; the work by Fox et al. [Fox93b] suggests that this assumption is valid for any device that is at least a distance 5jW L from any lateral edge. The surface of the substrate is assumed to be the only boundary that affects the thermal response of the device and it is considered to be adiabatic; thus, conduction through the interconnects and conduction/convection from the surface are neglected. Ignoring thermal energy transport from the substrate surface is supported by the work of Berger and Chai and Goodson et al. [Ber91, Goo95];
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32 however, they were mainly concerned with transport via convection to a surrounding gas (namely air). Nonetheless, for the regions of the device covered by oxide, it is unclear whether there is substantial heat conduction to this overlying oxide. From the analysis of Goodson et al. [Goo95], the devicetooxide thermal conductance is of the order of G = 4rk, which corresponds to an isothermal disk of radius r on the boundary of a semiinfinite medium of thermal conductivity k. Approximating the radius as */(WL)/7C and using the roomtemperature thermal conductivity of Si0 2 , the devicetooxide thermal conductance for a typical device is on the order of 1 x 10" 6 (W/Â°C). Comparably, the devicetosubstrate thermal conductance is on the order of 1 x 10" 3 (W/Â°C), showing that the majority of heat will flow through the substrate. The temperature rise at any point within the device can be described by the nonhomogeneous threedimensional heat conduction equation V2AT(x,y,z,t) + fc^Al) = l 3AT(xy,z,t) v J ' k a dt and the boundary conditions AT(Â±<Â», y, z, t) = (2.2) AT(x,Â±oo, z ,t) = (2.3) 3AT(x, y, z, t) dz = (2.4) z =
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33 AT(x,y,oo, t ) = 0, (2.5) where AT is the temperature rise above the local ambient (AT = TT ), g is the internal energy generation density, k is the thermal conductivity, a is the thermal diffusivity (a = k/(p Â• c ) where p is the density and c is the specific heat) and t is time. Typical values for the material properties are given in Table 2.1. Table 2.1 Semiconductor material properties Parameter
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34 using the Kirchoff transformation [Joy75], as discussed in Chapter Eight. Neglecting the spatial dependence of the thermal conductivity implies that the effect of dopant atoms is ignored. In the works by Weber and Gmelin and Goodson et al. [Web91, Goo95], the thermal conductivity of doped silicon (up to lxl0 18 and 1.7xl0 19 dopant atoms cm" 3 ) above 300 K is shown to differ only slightly from that of intrinsic silicon. Since the majority of the substrate is typically lowdoped semiconductor material, neglecting the doping effects on the thermal conductivity is reasonable. With the initial thermal conditions within the substrate specified as AT(x,y,z,0) = 0, (2.6) the solution to (2.1) can be expressed in the form AT(x,y,z,t) = 5f J dt'jG(x,y,z,tx',y',z',t')g(x',y',z' > t')dv' (2.7) t' = o v where G(x, y, z, tx', y', z, t) = exp 8[7CCC(tt')] L4cc(tt)J (xx) exp 2(yy') _4a(tt')_ exp (zz') 2 _4a(tt')_ + exp (z + z) 4a(tt')_ (2.8) is the Green's function for the given boundaryvalue problem [Ozi93]. Equation (2.8) is the solution to
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35 gj,5(xx')5(yy')5(zz')5(tt') I Â§9 a 9t (2.9) for the boundary and initial conditions given by (2.2) through (2.6), and physically represents the temperature at point (x, y, z) at time t, due to an instantaneous point source, g' (W s), of unit strength at point (x', y', z) at time t' . To account for the heatgeneration volume (V = W Â• L Â• H), (2.8) is substituted into (2.7) and integrated over the base/collector SCR, resulting in AT(x, y, z, t) = j" P(t') t' = o 8pcV H K L/2 + x ^ J L/2x erf . + erf V4a(ttV V4a(tt') W/2 + y + erf V4a(ttV V4a(tt') W/2y + erf Dz V4a(tt') + erf z + D + H */4a(tt') zD V4a(ttV V4a(ttV. D + Hz \1 , . + erf === dt (2.10) where g(x, y, z, t) = g(t') = P(t')/V , since the power dissipation is assumed to be uniform. Equation (2.10) represents the temperature response at any point in the device at time t due to a change in continuous power dissipation in the base/collector SCR. Assuming a step increase in power at t' = ( P(t') = P Â• U(t) ) and expressing the temperature rise as AT(t) = Z TH (t)P (2.11) yields the transient thermal impedance
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36 Z TH (x, y,z, t) = J" 8pcV crj / L/2 + x A  J L/2 x at /J erf AV^2 + yV erf AV^2y v V4at / v 74at fl 'z + D + m ,fDz erfl z= Â— 1+ erf V4at + erf , +erf 74at^ 74at D + Hz 74at dt (2.12) where the t Â— > oo value of the thermal impedance corresponds to the thermal spreading resistance R TH . Equation (2.12) represents the temperature rise at any point in the device normalized to a unitstep increase in power dissipation. For circuit simulation, a single temperature is needed to represent the effective operating temperature of the device. Fox and Lee [Fox91b] showed that the thermal impedance model evaluated at a surface corner of the emitter (x = L/2, y = W/2, z = 0) agreed well with measurements of the thermal spreading resistance R TH ; substituting these coordinates into (2.12) gives the following expression for the thermal impedance J TH <" I : erf ^U^=)U^M)crf( ! ;4pcV Kj4mJ WSatA VJ4 KXt 74 at dt (2.13) In this form, the thermal impedance model has four geometric input parameters. Of the four, three (W, L and D) are determined directly by the device layout. However, the fourth parameter, H, depends on the operating bias of the device. The thickness of the base/collector SCR, H, can be estimated using the
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37 depletion approximation; assuming a onesided step junction with uniform doping on each side gives 2 Â• e Si Â• e Â• (V R + â€¢ bi ) H = Sl Â° XT R ^, (2.14) V qN e P i with k R T ^bi = Tln ' N b Â• N ep , 2 (2.15) where Â£ Si is the dielectric constant of silicon, e is the permittivity of free space, V R is the reverse bias voltage on the base/collector junction, q is electronic charge, N is the doping level in the epicollector, k B is Boltzman's constant, T is temperature, N b is the doping level in the base, and nj is the intrinsic carrier concentration in silicon. Yjjj is the builtin potential of the base/collector junction. Equation (2.14) shows that the thermal impedance depends on the bias of the base/collector junction, and therefore can change during device operation. However, the squareroot dependence of H on the base/collector voltage, is relatively weak. Figure 2.3 illustrates the variation of the modeled thermal resistance with changes in the thickness of the base/collector SCR. The three data points plotted for each simulated device correspond to reverse bias base/collector voltages of 5, 10 and 20 V. The largest variation is observed for the smallest device, which shows a 25% change in its thermal resistance going from V R = V to 20 V. The larger devices show a weaker dependence on H and have no more than a 15% change in thermal resistance
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38 Â£ 20 x H c o oj 'C > 200 250 300 Variation of H (%) 350 400 Figure 2.3 Simulations showing the effect of variations in the thickness of the base/collector spacecharge region on the thermal impedance model (evaluated at steadystate) for different geometry BJTs. For each device, D = 0.35 urn, N epi = 1 x 10 16 cm" 3 and N b = 1.5 x 10 18 cm" 3 . The yaxis corresponds to the variation between the model evaluated at V R = V and the model evaluated at V R equal to 5, 10 and 20 V.
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39 going from V R = V to 20 V. However, at high base/collector biases, the maximum value of H becomes effectively independent of bias. As shown in Figure 2. 1 , typical bipolar technologies use a heavilydoped buried layer to reduce collector resistance. At high base/collector biases, the lowdoped epicollector region depletes down to the buried layer; consequently, the maximum value of H should be properly limited to the thickness of the epicollector. 2.2.1 Modification for Finite Wafer Thickness As previously derived, the thermal impedance model for singleemitter bulk BJT/HBT's represents the substrate as a semiinfinite halfspace. This representation assumes that the back side of the substrate does not affect the thermal response of the device. In general, this is reasonable since the basecollector junction is usually within 1 0.m of the substrate surface, and a typical wafer is between 350 to 800 im thick. However, wafers are commonly backlapped to improve thermal performance, and substrate thicknesses of 75, 80 and 100 nm have been reported by a number of authors [Kag94, Mar93, Liu95a]. As the wafer thickness is reduced, the substrate can no longer be approximated by a semiinfinite medium and the effects of the backside boundary must be taken into account. The threedimensional Green's function in the rectangular coordinate system can be represented by the product of three onedimensional Green's functions G(x, y, z, tx', y', z, t) = G x (x, tx', t') Â• G (y, ty', t') Â• G z (z, tz', t'). (2.16)
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40 The lateral boundaries are still assumed to extend infinitely and their effects on the thermal response are neglected; thus, the Green's function solutions in both the x and y directions remain unchanged. In the z direction, however, the substrate is now assumed to have a finite thickness D sub . The top surface of the substrate is still assumed to be adiabatic. The bottom surface of the substrate is assumed to be at a constant temperature, T(D sub ) = T , so that the temperature rise at this surface is defined by AT(D sub ) = T(D sub )T = 0. These boundary conditions define the new Green's function for the zdirection, which is given by G z (z,tz',t') = Â£ exp[aTip(tt')]Â— Â• cos(Ti p z) Â• cos(Ti p z') (2.17) P = i sub where r\ is the set of eigenvalues for the boundaryvalue problem and are given by the positive roots of cos(Ti p D sub ) = 0. (2.18) Equation (2.18) is solved when the argument of the cosine equates to odd multiples of 7i/2. Using equations (2.17), (2.16), (2.1 1) and (2.7), and then integrating over the base/collector SCR, assuming a unitstep increase in power at t' = 0, gives the following expression for the thermal impedance at any point in the device
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41 fL/2 + \\ JL/2x ft >\ f Ql r L/Z + X J\^/lWu,) = {4^K^rJ +erf i^si 74at / v 74at i. ~ 2cos(r p z)exp(arpt) Â•{sin[Ti p (D + H)]sin[ri p D]} (2.19) where V = W L H and n p = &Â£^ (2.20, Evaluating (2.19) at the coordinates (x = L/2, y = W/2, z = 0) to give a single effective operating temperature, results in the following expression for the thermal impedance Z TH (t) = f^erffkArf. " 2exp(arTt) Â• X n D (sin[T 1p (D + H)]sin[T 1p D]}, (2<21) , lp sub Since (2.21) is derived from the physical heat conduction equation, it can be used to anticipate the effects of substrate scaling on the thermal impedance. Figure 2.4 illustrates equation (2.21) evaluated at various values for D sub . The results show that the thermal resistance decreases as the substrate thickness is reduced, which agrees with the trend predicted by Hattori et al. using a threedimensional numerical simulator [Hat95]. Figure 2.4 also shows that (2.13) provides
PAGE 51
42 675 650 " 625 X
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43 an accurate prediction of the thermal resistance over most of the range of substrate thicknesses; only when the substrate thickness is significantly reduced (< 100 (J.m), is there a large deviation between the two models. 2.2.2 Effects of Interconnect Metallization on the Thermal Impedance For the derivation of the BJT/HBT thermal impedance model, the surface of the substrate is assumed to be adiabatic. In actual devices, portions of the base, collector and emitter regions are in direct contact with the metallization used to electrically connect different devices on a chip. Since the metallization typically has a high thermal conductivity, it is possible that the heat conduction via the interconnects significantly influences the thermal response of a device. Therefore, the validity of such an assumption should be investigated. Threedimensional (3D) finiteelement (FE) thermal simulations of a bipolar transistor, using the ANSYS software package [Ans96], were performed to examine the effects of the interconnect metallization on the thermal impedance. To simplify the FE model, the device was considered to be symmetric in both lateral directions; therefore, only one quarter of the device was simulated. The bottom and exterior sides of the substrate were assumed to be at a fixed ambient temperature. The top and side surfaces of the interconnects, as well as the top surface of the interlayer dielectric, were assumed to be adiabatic. The FE simulations tend to overpredict the heat conduction through the interconnects since any contact resistances at the material interfaces were neglected. The assumed symmetry of the device implies that the base and collector metallization are equidistant from the emitter. In typical
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44 devices, the collector contact is offset a greater distance from the emitter than the base contact. Typical ranges for these offsets are 0.5 to 10 Lim between the base and emitter contacts, and 2.5 to 25 um between the collector and emitter contacts [Gra93]. While the FE model does not exactly represent any actual device structure, it can provide an estimate for the significance of the heat flow through the interconnects as a function of their distance from the active device. Figure 2.5a shows the FE model for bipolar devices with full metallization. Steadystate thermal simulations were run for various interconnect spacings; this spacing corresponds to the edgetoedge distance between the emitter and base/collector interconnects. Simulations were also run of the same structure with the base/collector interconnect removed. The results of the two groups of simulations were compared to determine the effect of the base and collector interconnects on the thermal resistance. Figure 2.5b shows the results of the comparison between the FE simulations. The data clearly shows that the effect of the base/collector interconnect metallization is small and decreases as the interconnects are moved away from the active device area. The collector interconnect has less of an effect on the thermal impedance than the base interconnect, due to the larger distance between the collector contact and the active device. In any case, the effect of either the base or collector interconnect should be negligible compared to the influence of the emitter metallization. To determine the extent of the effect of the emitter interconnect on the thermal impedance, steadystate thermal simulations were run for different devices with only the emitter metallization in contact with the device. Figure 2.6a shows the
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45 (a) 2.5 8 20 Pi 15 03 0> _c c o 4Â— > > 1.0 0.5 0.0 9 Â— OL = 4 urn, W = 1 (im 3 Â— QL = 4 (im, W= 1.8 \Lm AL = 8 lm, W = 1 fim 0.5 2.5 3.5 Interconnect Spacing (fim) (b) 5.5 Figure 2.5 ANSYS simulations showing the effect of emitter, base and collector interconnects on the thermal resistance. The device specifications are D = 0.2 (im and H = 0.35 fim, the interconnect width W met = 2 ^m and thickness d met = 0.9 (im, and the interlayer dielectric thickness d ox = 0.7 (im: a) The finiteelement model simulated with ANSYS; b) the variation between the thermal resistance accounting for emitter, base and collector interconnects and the thermal resistance accounting for only the emitter interconnect, plotted as a function of the spacing between emitter and base/collector interconnects.
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46 (a) 30 Â£
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47 FE model for devices with only the emitter metallization. The same devices were also simulated with the emitter interconnect removed. The simulations were performed by independently varying each structure parameter of the FE device model. Reasonable values were chosen for each parameter to represent a nominal device design; each parameter was varied about the nominal value to represent a reasonable range of technology scaling. Figure 2.6b shows the results of the FE simulations. The emitter metallization becomes a more effective path for heat evacuation as the thickness, d met , and the width, W met , of the interconnect increase and as the thickness, d ox , of the dielectric layer between the substrate and the interconnect decreases. The data also show that the effect of the emitter interconnect increases as the depth of the base/ collector junction is decreased (the heat source is moved closer to the surface) and as the length of the emitter is decreased. Transient thermal simulations of the FE model in Figure 2.6a were used to examine the effect of the emitter interconnect on the transient thermal response. ANSYS was used to simulate the structure with and without the emitter interconnect in contact with the device; the results are shown in Figure 2.7. The thermal responses for the device with and without the interconnect match until significant heat reaches the surface of the device. The time for heat to reach the surface of the device can be approximated as the square of the distance D divided by the thermal diffusivity of the substrate material. The resulting time is approximately 0.44 nanoseconds, which agrees with the FE simulations. The adiabatic boundary condition of the device without the interconnect predicts a larger response since the heat is completely reflected once it reaches the surface. The device with the emitter metallization, which
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48 1.5 U o g 1.0 o
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49 acts as a separate heat sink path, has a reduced thermal impedance and an effectively slower thermal response. Based on the results of the 3D FE simulations, neglecting the base and collector interconnect metallization in the model derivation is reasonable since it only slightly affects the thermal impedance of a device. The emitter interconnect, however, has a greater influence on both the steadystate and transient thermal responses. The effect on the thermal resistance will be more significant for devices with smallgeometry emitters and shallow base regions, where the transient thermal response will mainly be affected for large devices with substantial contact structures. In either case, equations (2.13) and (2.21) will tend to overpredict both the steadystate thermal resistance and the transient rise of the thermal impedance. 2.2.3 A Model for the Thermal Impedance of the Emitter Interconnect As shown in the previous section, the assumption that the top surface of the device is adiabatic neglects heat flow in the emitter interconnect and results in a thermal impedance model that overestimates the transient temperature rise in a bipolar device. To model the effects of the emitter interconnect on the overall thermal impedance, both the thermal resistance and thermal capacitance of the metallization need to be considered. The thermal resistance of the emitter metallization is derived by assuming that the interconnect can be represented by a onedimensional cooling fin, so that the temperature rise at any point x met along the interconnect, AT me t( x me t ) = T met (x met ) T , can be approximated by
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50 a 2 AT 3x met 2 . ry, _ m met AT met = Â° (2.22) met The second term on the lefthand side of (2.22) accounts for heat conduction through the underlying oxide as the heat travels along the interconnect, where 1 k rl met u met in met met (2.23) is the characteristic thermal length in the interconnect and met (2.24) is the heat transfer coefficient from the interconnect to the substrate. The material properties for the emitter interconnect are given in Table 2.2. Table 2.2 Emitter interconnect* material properties Property met Pmet 'pmet Definition Thermal conductivity Density Specific Heat Source: [Ozi93] * Assumed to be aluminum Value 2.39 (W cm" 1 K" 1 ) 2.7 (g cm" 3 ) 0.9 (J g" 1 ^ 1 )
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51 Approximating the temperature in the interconnect using a onedimensional equation implies that the temperature gradients in the vertical and lateral directions within the emitter interconnect are negligible. The validity of such an assumption can be evaluated using the Biot number, which corresponds to the ratio of the internal and external thermal resistances of a given object [Ozi93]. If the Biot number for the interconnect is much less than unity, then the interconnect can be approximated as a onedimensional thermal medium. The vertical and lateral Biot numbers for the emitter interconnect are given by B Vmet = h met d met /k met and B Lmet = n met w met / ( k met d met)' respectively. For most practical metallization geometries, the Biot numbers are much less than one and the coolingfin model is an accurate representation of the emitter interconnect. Assuming that the temperature rise in the interconnect at the emitter contact is equal to the effective operating temperature of the device, and that the temperature rise approaches zero far from the contact, the thermal resistance of the emitter interconnect can be expressed as R THmet = ^met"^^!^^*] 1 Â• (225) The thermal capacitance of the emitter metallization can be approximated as ^THmet = Pmet c pmet* met (2.26) The volume of the metallization is V met = W L 5 met , where 8 met represents the effective length of the interconnect structure. The parameter 8 met should be evaluated to include the volume of the contact and interconnect metallization but can
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52 also be extracted from transient thermal measurements or numerical simulations. Once the thermal resistance and thermal capacitance have been calculated, the transient thermal impedance of the emitter interconnect can be approximated by Z THmet( t ) R THr ='['" exp t 'met'' (2.27) where T met = RTHmet^THmet Â• ^ ne overa ll thermal impedance of a bipolar device can now be represented by the parallel combination of two thermal impedances, such that effectively ^th( s ) Â— ZTHdev( S ) ' Z THmet (s) Z THdev( S ) + Z THmet( S ) (2.28) where Z THdev (s) is determined from the transient thermal impedance given by either (2.13) or (2.21). 2.2.4 Effects of Isolation Structures on the Thermal Impedance While junctionisolated technologies are still used, the drive to increase packing density, improve lateral isolation and increase device operating speeds has led to the development of newer isolation technologies for VLSI bipolar applications. The advanced isolation technologies typically used in bulk bipolar fabrication are recessed LOCOS (local oxidation of silicon) and Ugroove [Wol90, Gra93]; Figure 2.8 illustrates examples of bipolar devices fabricated with these isolation techniques. Since advanced isolation structures typically use low conductivity
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53 Collector psubstrate (a) Emitter o Collector psubstrate (b) Figure 2.8 Crosssections of typical BJT's fabricated with advanced isolation technologies: a) Recessed LOCOS; b) Ugroove isolation.
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54 materials like Si0 2 , the thermal impedance of a device using such isolation tends to be higher than that of its junctionisolated counterpart. The bulk BJT/HBT thermal impedance model treats the substrate as a homogeneous material; therefore, it is unclear whether the thermal impedance model is applicable to devices which are fabricated with advanced isolation. Threedimensional (3D) finiteelement (FE) thermal simulations, using ANSYS, were performed to examine the effects of advanced isolation structures on the thermal impedance of bipolar transistors. Two FE models were developed to separately investigate the effects of recessed LOCOS and Ugroove isolation. To simplify the FE models, the device was considered to be symmetric in both lateral directions, so that only one quarter of the device was simulated. The bottom and exterior sides of the substrate were assumed to be at a fixed ambient temperature. The top surface of the device was assumed to be adiabatic. Due to the assumed symmetry, the active device region was surrounded on all sides by the isolation structure, which was at uniform distance from each side of the emitter. As shown by the illustrations in Figure 2.8, the distance between the isolation structure and the intrinsic device is not uniform on all sides of the device. Typical values for the distance between the emitter and the isolationÂ— for the portions of the isolation structure immediately surrounding the emitterÂ— are in the range from 0.3 fim to 0.8 im for advanced bipolar devices [Del91, Klo93, Yam93, Pru94]. The distance between the emitter and the portion of the isolation structure on the far side of the collector contact is generally larger, typically two to four microns [Del91, Klo93]. For both FE models, the sidewalls of the isolation structures were perpendicular to the top surface of the substrate.
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55 For typical Ugroove isolation, the trench is created by anisotropic etching and the sidewalls are nearly perpendicular to the surface. However, actual LOCOS structures have tapered edges (see Figure 2.8) that get progressively thinner toward the active device. To determine the implications of the model's nonphysicality, twodimensional (2D) FE simulations were run for various angles (30 to 90 degrees) between the substrate surface and the sidewall of the isolation. The simulations showed that the temperature rise increased as the angle increased; thus, the 3D LOCOS model should show a larger effect than that of an actual isolation structure. While the finiteelement models do not truly represent the physical device layout, they allow an orderofmagnitude estimate for the effects of the isolation structures on the thermal impedance. Steadystate thermal simulations were run for various deviceisolation spacings, corresponding to the edgetoedge distance between the emitter and the isolation structure. For the Ugroove isolation model, this spacing is the distance between the emitter and the edge of the surface LOCOS; the actual trench is assumed to be an additional 0.5 im away from the edge of the LOCOS [Del91, Yam93]. Simulations were also run for the same devices with the isolation structures removed. LOCOS isolation is formed by selectively oxidizing regions of the semiconductor substrate in a dry or wet oxygenrich ambient. For bipolar technologies, the resulting Si0 2 structures are typically no more than one micron thick, since the growth of thicker oxides is impractical [Wol90, Gra93]. Figure 2.9a illustrates the FE model for bipolar devices with recessed LOCOS isolation. The oxide was assumed to be fully recessed beneath the top surface of the substrate and
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56 (a) 1.0 1.5 2.0 2.5 DeviceOxide Spacing (im) (b) 3.0 3.5 Figure 2.9 ANSYS simulations showing the effect of recessed LOCOS isolation on the thermal resistance. The device specifications are L = 2 u.m, W = 1 im, D = 0.35 u\m and H = 0.35 im: a) The finiteelement model simulated with ANSYS; b) the variation between the thermal resistance accounting for the isolation and the thermal resistance assuming a homogeneous substrate, plotted as a function of the edgetoedge spacing between the emitter and the isolation.
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57 had a thickness, d tox , of one micron. Figure 2.9b compares the FE simulations with and without the isolation. The effect of the LOCOS can be significant at small deviceisolation spacings, but decreases as the isolation is moved away from the active device region. In Figure 2.8a, the portions of the LOCOS structure close to the emitter have the largest effect on the thermal response, since they directly restrict the lateral heat flow away from the device. A number of manufacturers are using thinner standard or semirecessed LOCOS (0.3 to 0.6 pm) combined with junction isolation to reduce fabrication times and improve compatibility with existing MOS technologies [Klo93], [Pru94]. The thinner oxides have a smaller effect on the thermal resistance, and therefore, the FE simulations can be considered worstcase. Ugroove isolation differs from LOCOS in that trenches are etched directly into the substrate and then backfilled with oxide and polysilicon. The depth of the trench, d tr , is typically on the order of 3 pm [Yam93, Ona95], but has been as large as 5 pm [Del91]; the width of the trench is generally in a range from 0.6 to 1.5 pm [Del91, Yam93, Ona95, Shi96]. Ugroove trenches will typically have a surface LOCOS layer, but the thickness of this layer is usually no greater than 0. 1 to 0.15 pm [Yam93], since the isolation is mainly achieved by the trench. Figure 2.10a shows the FE model for devices with Ugroove isolation. The thickness of each fill layer ( d trox for oxide and d , for polysilicon) in the Ugroove was assumed to be uniform. Figure 2.10b compares the FE simulations with and without the isolation. The effect of the Ugroove isolation on the thermal resistance is greater for small deviceisolation spacings than in LOCOS due to the larger depth of the trench.
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58 (a) 1.0 1.5 2.0 2.5 3.0 DeviceIsolation Spacing (urn) (b) 3.5 4.0 4.5 Figure 2.10 ANSYS simulations showing the effect of Ugroove isolation on the thermal resistance. The device specifications are L = 2 urn, W = 1 urn, D = 0.35 urn and H = 0.35 urn. The Ugroove specifications are d tr = 3.5 am, d trox = 0.38 urn and d poly = 0.75 urn: a) The finiteelement model simulated with ANSYS; b) the variation between the thermal resistance accounting for the isolation and the thermal resistance assuming a homogeneous substrate, plotted as a function of the edgetoedge spacing between the emitter and the Ugroove isolation.
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59 However, these results represent the worst case, since in an actual device the active region is not immediately flanked by the Ugroove on all sides. Transient thermal simulations of the FE models shown in Figure 2.9a and Figure 2.10a were used to examine the effects of both LOCOS and Ugroove isolation on the transient thermal response. ANSYS was used to simulate the device with and without the isolation structures; the results are shown in Figure 2. 1 1 . As the heat travels laterally and reaches the edges of the isolation structure, the response accounting for the isolation begins to deviate from the response without the isolation. The time for the heat to reach the edges of the isolation structures can be approximated as the square of the deviceoxide separation (1 Jim) divided by the thermal diffusivity of the substrate material; the resulting time is on the order often nanoseconds, which agrees with the simulations of both the LOCOS and Ugroove isolation. The oxide used in the isolation structures restricts the lateral flow of heat away from the device and in both cases results in a larger temperature rise. Based on the results of the 3D FE simulations, advanced isolation structures such as recessed LOCOS and Ugroove can considerably increase the thermal impedance of bipolar devices. In most cases, the bulk bipolar model will tend to underpredict both the steadystate and transient thermal response of devices fabricated with oxidebased isolation structures. The error in the model will be the greatest for advanced, highlyscaled devices fabricated with deep trench isolation.
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60 2.0 1.5 U a 8 i.o c T3 U E 2 0.5 c3 E t> u H Â© Â— Â©Without Isolation Q Â— QWith Isolation 0.04 10" 1 10 4 10" Â£ u 3 o c 3 O 2 ~ 1 rt Â©Â—Â©Without Isolation Q Â— QWith Isolation ?*r 10 B10" 10" Figure 2. 11 ANSYS simulations showing the effect of advanced isolation structures on the transient thermal impedance. The deviceisolation spacing is one micron. The specifications for the device structure are L = 2 im, W = 1 (im, D = 0.35 urn and H = 0.35 im: a) Recessed LOCOS or BOX isolation with d fox = 1.0 (im; b) Ugroove isolation with d tr = 3.5 u\m, d lrox = 0.38 im and d poly = 0.75 im.
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61 2.3 Verification of the SingleEmitter Thermal Impedance Model To verify the thermal impedance model, threedimensional (3D) finiteelement (FE) simulations of a junctionisolated BJT were performed using ANSYS. Interconnect metallization was neglected and the substrate was assumed to be homogeneous silicon with the bulk properties given in Table 2. 1 . The FE simulations were evaluated at the surface corner of the emitter and compared to the singleemitter thermal impedance model given by equation (2.21); the results are shown in Figure 2.12. The analytic model agrees closely, for both the steadystate and the transient, with the 3D FE simulations for both device geometries. The predicted values for the steadystate thermal resistance agree within twelve percent of the FE simulations. The error can be partially attributed to numerical error associated with the FE mesh. The model was also compared to measured thermal impedances. The measured data were extracted using the basethermometry technique developed by Zweidinger et al. [Zwe96]. Figure 2.13, Figure 2.14 and Figure 2.15 compare the measured and simulated data for the transient thermal impedance of Harris HBC bulk BJTs. The thermal impedance model does a good job of predicting the steadystate thermal resistance, with no more than a 20% error between the model and the measurements. The model given by (2.13) tends to overpredict the transient response. As shown with the ANSYS simulations in Figure 2.7, this discrepancy can be attributed to the model's neglect of the emitter metallization. When the thermal impedance of the emitter interconnect is accounted for, with 8 met = 50 im extracted
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62 TEMPERATURE (Â°C): C3 KXXXXXXXJt WTTTTTT ESI :x;:x::x::x:l k ;;;; ;;;w;.';;,;l 27 27,431 27.863 28,294 28.725 29,157 29,588 30,019 30.451 30,882 (a) 1150 P 950 ^ 750 
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63 U u c a C3 180 130 80 30 20 Measurement 00 Model: Without Emitter Int Â•Model: With Emitter Int. 10 10 .^@::~ 10" .Â•Â•Â£!}' 10" u X c o o n 60 50 40 30 20 10 10 Measurement Â©Â•OModel: Without Emitter Int. Model: With Emitter Int. 10 10 10" Figure 2.13 Measured and simulated data for the transient thermal impedance of Harris HBC bulk BJT's with W = 2 ^m: a) L = 30 urn; b) L = 100 u.m.
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64 U 300 220 g 140 03 U s 03 U 60 20 10 10 & \ ,::::::::& Â— :: = : = Â© = Measurement iL 0OModel: Without Emitter Int. Model: With Emitter Int. io10" b Time (sec) (a) 10 4 io140 u o o c 03
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65 260 220 Measurement Â©OModel: Without Emitter Int. Model: With Emitter Int. 8 :::: = Â© = :@::::
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66 from the measurements, the model provides a more accurate representation of the transient thermal response. 2.4 Derivation of the MultipleEmitter BJT/HBT Thermal Impedance Model The thermal impedance model for bulk MEBJT/MEHBT's is an extension of the singleemitter model. A multipleemitter device consists of singleemitter devices placed adjacent to each other along their lengths. Since there are multiple devices (referred to as "emitter fingers") that are thermally coupled through the substrate operating in close proximity, the temperature rise in each emitter finger is affected not only by its own power dissipation, but also by the power dissipated by its neighbors. The heat conduction equation, (2.1), is linear, so superposition can be used to calculate the total temperature rise in the device. The equation for the temperature rise can then be manipulated to provide expressions for the effective temperature rise in each individual finger. Figure 2.16 illustrates the simplified multipleemitter device geometry assumed for the model derivation. The substrate is represented by a homogeneous semiinfinite halfspace with an adiabatic top surface with multiple imbedded heat sources. The emitter fingers are assumed to be uniform in size and shape, with width W and length L. Each finger has a corresponding heat source, due to an assumed uniform power generation in the base/collector SCR; each heat source has a thickness H and is displaced a distance D below the surface of the substrate. As with the singleemitter model, D is assumed to equal the depth of the base/collector junction
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67 Figure 2.16 The simplified device geometry used to define the solution domain for the bulk, multipleemitter BJT/HBT thermal impedance model. The substrate is represented by a semiinfinite halfplane with an adiabatic surface. Each emitter finger has a width W and length L and each heat source (the rectangular volumes) is displaced a distance D below the surface of the device and has a thickness H. The distance D is equivalent to the depth of the base/collector junction and the thickness H is approximated by the thickness of the base/collector SCR. The emitter fingers are uniformly spaced with and edgetoedge separation distance S .
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68 and H can be calculated using equations (2.14) and (2.15). The edgetoedge separation, S, between adjacent fingers is assumed to be uniform. The Green's function technique can be employed to find the temperature rise within the device. By applying superposition, the solution is expressed as the sum of the Green's function solutions for the multiple heat sources n t AT(x,y,z,t) = X? j dt'JG(x,y,z,tx',y',z',t')g(x',y',z',t')dv'. (2.29) 1 .' = v where G(x, y, z, tx', y', z', t) is given by equation (2.8). The summation accounts for the integration over the different spatial coordinates of each heat source. To clarify the derivation, certain conventions and definitions can be established. The origin for the coordinate system is fixed at the center of the leftmost finger at the surface of the device. A device is considered to have a total of n emitter fingers and a reference order is established with the fingers numbered sequentially starting from the leftmost finger. The character j , where j = 1 Â— > n , is used to reference a specific emitter finger. The ith neighbor (where i = 1 Â— Â»n1) of a given emitter finger, EFj , is defined as a finger situated an edgetoedge distance [iS + (i 1)W] away on either side. Using equations (2.8) and (2.29), the temperature rise at any point in the deviceassuming a step increase in power at t' = for each fingerÂ— is given by
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69 AT(x, y, z, t) = 'L/2 x ^ r *jdt r JL/2 + x\ /L/2 . r crf ry(2j3)w/2(ji)s + erf 74at y + (2jl)W/2 + (jl)S 74at ,,'z + D + H^ /Dz erf == Â— + erf V4at + erf I Z , )+erf V4atV 74at D + Hz 74at (2.30) which accounts for n heat sources, one for each emitter finger EFj . Equation (2.30) can be manipulated to provide the temperature rise in each emitter finger. As with the singleemitter model, the temperature rise in each finger is represented by a single effective value. To simplify the derivation, symmetry is assumed such that the distance from the effectivetemperature point of finger EFj to the heat source of its i th neighbor, is the same as the distance from the effectivetemperature point of the ith neighbor to the heat source of EFj . This symmetry is attained only for the coordinates (x, y = [j 1 ][S + L], z). When (2.30) is evaluated at each of these points, the model is reciprocal and the effective temperature rise in each emitter finger, AT EF : , can be expressed as
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70 AT AT EFl EF2 AT EFn J C1 J C1 ... z ... z _ Z C(nl) Z C(n2) C(nl)
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71 Z Ci (x, z, t) ^ J8pcVL ,, L/2 + x^ JL/2x erf Â— ==^ +erf j = it 74at [ erf l f(W/2 + i(W + S)) 74at 74at i + y(w/2i(w + s)) ^/4at n 'iÂ±DÂ±HVerff^z V4at / V V4at D + Hz + erf[ Z , l+erf 74at 74at (2.33) and accounts for the portion of the temperature rise in a finger due to the power dissipated by its ith neighbor. Thus, for the assumed symmetry, the thermal impedance of a device with n emitter fingers can be described with a single self impedance and (n1) coupling impedances. Equations (2.32) and (2.33) should be evaluated at a single point to represent the temperature rise of each finger by a single effective value. To keep the MEBJT/MEHBT model as similar as possible to the singleemitter model, the points x = L/2 and z = are used, giving z s (t) = J 1 :erf D + H r_j^WÂ— y erfl 2pcV \j4atJ V4atA ^ J4a erf D 74at dt (2.34) and Z Ci (t) = MpcVL 4pcVL Â£r I74at [ erf f(W/2 + i(W + S))V erf [ (W/2i(W + S)) 74at erf[ DÂ±H)_er/ D V4at (2.35)
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72 as the final expressions for the self and coupling impedances. Therefore, the overall selfheating on the scale of the entire device can be described by the selfheating and thermal interactions on the smaller scale of each individual emitter finger. Accounting for a finite wafer thickness can be important for multipleemitter devices since the coupling impedances decrease as the wafer thickness is reduced [Daw94], [Hat95]. The multipleemitter model can be modified in a similar fashion as that for the singleemitter model; by simply using equations (2.17) and (2.20) in place of the G z (z, tz', t') in equation (2.29), the expressions for Z s and Z Cj will now account for a finite wafer thickness. Since the multipleemitter thermal impedance model is simply an extension of the singleemitter model, the effects of interconnect metallization and advanced isolation technologies are not taken into account. Neglecting these portions of the overall device structure is assumed to affect the multipleemitter model in the same manner, and to the same extent, as to which it affects the singleemitter model. 2.5 Verification of the MultipleEmitter Thermal Impedance Model Twodimensional (2D) finiteelement (FE) simulations of a junctionisolated, threefinger BJT were performed using ANSYS to verify the multipleemitter thermal impedance model. Twodimensional FE simulations were used instead of 3D simulations due to limitations of the available version of ANSYS. The validity of comparing 2D FE simulations to a 3D analytic model is established by evaluating the thermal impedance model derived for both two and three dimensions.
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73 Figure 2.17a compares the results, which show that the 3D the 2D models converge for long devices. The difference in the predicted thermal resistance values decreases from 22% to less than 1% as the length of the device is increased from 50 im to 800 (im. Consequently, the 2D FE simulations can verify the 3D thermal impedance model evaluated for devices with long emitters. The 2D FE simulations do not verify the model for shorter devices where the heat flow becomes threedimensional. However, the verification of the singleemitter thermal impedance model for 3D heat flow can be assumed to also verify the MEBJT model. This assumption is reasonable since the physics that describe the singleemitter model also apply to the MEBJT thermal impedance model. The physical device was assumed to be symmetric so that the FE model represented only half of the device. Figure 2.17b shows an illustration of the FE model simulated with ANSYS. Interconnect metallization was neglected and the substrate was assumed to be homogeneous silicon with the bulk properties given in Table 2.1. The bottom and exterior side of the substrate were held at a constant ambient temperature while the top surface and the interior side were assumed to be adiabatic. The FE simulations were compared to the multipleemitter thermal impedance model given by equations (2.34) and (2.35), accounting for a finite substrate thickness; the results are shown in Figure 2.18. The analytic model agrees well, in both the steadystate and transient, with the 3D FE simulations of the self and coupling impedances. The predicted values for the steadystate thermal resistance agree within three percent of the FE results, which is within the expected error of the model and the numerical simulations.
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74 U o 250 200 x O a Oh rt o 50 100 50 O Â— Â©2D Model: L = 50 am O03D Model: L = 50 urn a Â— a 2D Model: L = 200 fxm Qa 3D Model: L = 200 Jim A Â— A2D Model: L = 800 Llm AA3D Model: L = 800 ^m O 10 12 W Â£Ji 10 10 fi , .O ';.g;A .ET' e Â— e Â— e Â— ejO Â— Â€>ooo,a* Â— Ata^gS &BB J .Â£ S .^ * r .2!^ t .A^!v^10" 10" 6 Time (sec) (a) 10" 10" 10 ( TEMPERATURE (Â°C): 27 29,072 31,145 33.217 35.289 37,361 39,434 41,506 43.578 45,651 (b) Figure 2.17 Twodimensional heat flow in multipleemitter bipolar transistors: a) A comparison of the threedimensional thermal impedance model to a twodimensional model for W = 1 im, D = 0.5 \xm and H = 0.5 im; b) the finiteelement model simulated with ANSYS for P = 500 uW.
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75 15 U o o c a E 5 "c5 1 1 OZ s : 2D ANSYS Z C1 : 2D ANSYS AZ S +Z C2 : 2D ANSYS Z s : Model
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76 2.6 Summary A thermal impedance model for bulk singleemitter BJT/HBT's was presented and then extended for devices with multiple emitter fingers. The model was shown to agree reasonably well with threedimensional finiteelement simulations and measurements of junctionisolated devices. The effects of interconnect metallization and advanced isolation technologies on the thermal impedance were investigated; a simple model for the thermal impedance of the emitter interconnect was demonstrated. The results suggest that the model can be expected to provide reasonable predictions for the thermal impedance of junctionisolated devices. However, for highlyscaled devices, the effects of advanced isolation can be significant and the accuracy of the model will decline. Methods for modeling the effects of isolation structures are proposed in Chapter Eight.
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CHAPTER 3 A CIRCUIT MODEL FOR THERMAL COUPLING AND A LUMPED ELECTROTHERMAL MODEL FOR BULK MULTIPLEEMITTER BIPOLAR TRANSISTORS 3.1 Introduction Due to increased interest in the role of thermal effects in device and circuit operation, especially for silicononinsulator (SOI) and heterojunction technologies, circuit simulators and compact device models have been modified to account for the dynamic temperature response within a device [McA92, Fox93b, Fos95]. Most of the implementations have been applied to the case of selfheating, where a device's effective operating temperature (EOT) depends on its power dissipation only. In many circuits and some devices, such as multipleemitter bipolar transistors, a number of devices can operate in close proximity. Under such conditions, the EOT of a device is no longer determined solely by its own power dissipation but also depends on the operation of its neighbors. Therefore, not only must circuit simulators (and compact device models) be able to model dynamic selfheating, they must also be able to model the dynamic thermal coupling between individual devices or portions of one device. An approach for modeling crosschip thermal coupling using a circuit simulator was described by Fukahori and Gray [Fuk76]. The thermal coupling between devices in an arbitrary circuit was modeled using a finite difference 77
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78 technique. The semiconductor substrate was represented by a threedimensional numerical mesh with equivalent thermal resistances and capacitances. The electrical elements in the circuit (transistors, etc.) were represented by their standard compact circuit models. The values for the lumped thermal components were calculated by discretizing the heat conduction equation using a finite difference approximation. In [Mar93], a similar approach was presented and applied to the simulation of multipleemitter HBT's. In this case, twoport theory was used to generate a finite twodimensional resistance network that represented steadystate heat conduction in the substrate. For both applications, the resulting circuit admittance matrix contained elements corresponding to the electrical circuit and also the thermal elements. The NewtonRaphsonlike iteration scheme of the modified circuit simulators was then used to solve the coupled electrothermal problem. To simulate both interdevice thermal coupling and selfheating using this method, a large number of thermal nodes is required; therefore, this approach can drastically increase simulation time. Chapter One described a common method for using thermal impedances to efficiently model selfheating in circuit simulators. A logical progression would be to expand this method to account for thermal coupling between devices. Such an approach can provide a more efficient alternative to the seminumerical methods mentioned above. This technique was applied by Moinian et al. for modeling crosssubstrate thermal coupling in bipolar circuits [Moi94], and by Baureis for modeling multipleemitter HBT's [Bau94]. However, their circuit implementations did not correctly represent the thermal interactions between (or within) the devices. The shortcoming of the coupling model used in these works is discussed in this chapter.
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79 A circuit model is then presented which correctly models thermal coupling and is compatible with the selfheating circuit model described in Chapter One. Once a valid circuit model for thermal coupling has been developed, it can be used with the multipleemitter thermal impedance model to perform both steadystate and dynamic electrothermal simulations of multipleemitter BJT/HBT's. The multipleemitter thermal impedance model expresses the selfheating of an entire device as the sum of the thermal actions and interactions of the individual emitter fingers. The thermal model structure requires that a single multipleemitter device be represented by multiple compact device models. While this configuration allows for the examination of the EOT of each finger in a device, for devices with a large number of emitter fingers, the overall electrothermal network can become complex enough to make moderateto largescale circuit simulations impractical. To make the multipleemitter electrothermal model more suitable for circuit simulation, its complexity can be reduced by representing the overall thermal response of the device by a lumped thermal impedance. The lumped thermal impedance is generated by applying the measurement approach developed by Zweidinger et al. to the simulation of the complete electrothermal model [Zwe96]. The thermal impedance extraction technique is briefly reviewed in this chapter. The lumped model generation procedure is then described and the results are compared to the complete electrothermal model.
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80 3.2 A Circuit Model for Thermal Coupling The EOT of any device in a system of n thermally coupled devices (e.g. a multipleemitter bipolar transistor with n emitter fingers) can be expressed as T DEV1 (t) = [AT 1 (t)+AT 12 (t) + +AT ln (t)]+T amb T DEV2 (t) = [AT 21 (t) + AT 2 (t) + +AT 2n (t)]+T amb T D EVn(t) = [AT nI (t) + AT n2 (t) + +AT n (t)]+T amb (3.1) where ATj(t) = Â£' ] [Z Sj Â• Pj(s)] and AT^t) = Â£ _1 [Z Cji Â• Pj(s)] . The impedance Z Sj is the self impedance of device j , and Z Cji represents the coupling impedance between device j and device i . (In general, it is not necessary for Z Cji to equal Z cj : .) The modifications described in Chapter One allow circuit simulators to model selfheating; therefore, the EOT of each device in a simulation is calculated by T DEVj (t) = ATjW+T^ (3.2) and is independent of its neighbors. The obvious way to expand this technique to account for interdevice thermal coupling would be to simply tie together the temperature nodes of individual devices using coupling impedances; this approach was used by Baureis and Moinian et al. [Bau94, Moi94]. Figure 3.1 shows an example of such a thermal coupling network for two devices, where Z c = Z C12 = Z C21 . Unfortunately, simple analysis of the circuit in Figure 3.1 shows that it does not correctly model the expression in (3.1). For example, analyzing
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T DEVl(t) Pl(t) ambl T DEV2(t) P 2 (t) Figure 3.1 A thermal coupling circuit model for two devices. The temperature nodes of the two thermally coupled devices are connected using a thermal coupling impedance.
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82 the circuit in the steadystate limit gives the following expression for the EOT of device 1 T M L *> l p + M a p +T ex x\ 1deV! " (R c + R sl + R S2 ) Hl+ (R c + R SI+ R S2 )^ 2+lamb (3 ' J) A similar expression can be derived for the EOT of device 2. The problem with this network formulation is that when individual temperature nodes are connected through an impedance path, the entire network becomes distributed among the coupled devices. The self impedances and coupling impedances, as derived, are not defined to be distributed elements. In a more simplistic view, the network in Figure 3.1 does not properly constrain the paths of the respective device powercurrents. The powercurrent of a given device is divided between its own self impedance and the rest of the network. The portion of that device's power flowing through its neighbor's self impedance has no physical meaning. As a result, the voltages generated at the temperature nodes do not correspond to the correct device temperatures. To develop a correct circuit representation of (3.1) and avoid the shortcomings of the aforementioned coupling technique, control sources can be utilized in a thermal coupling network group composed of two subnetworks. Each device in a group of n thermally coupled devices has its own network group. Figure 3.2 demonstrates how a thermal coupling network group works. Subnetwork A attaches directly to the temperature node of device 1. The currentcontrolled current source (Fj ) in subnetwork B has unity gain and is controlled by the current
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TT E 12 (t) Ei 3 (t) subnetwork A Em(t)
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84 flowing through the voltage source V, in subnetwork A. In this example, V , is also used to set the reference ambient temperature. The voltage drop across each coupling impedance (Z Cil ) in subnetwork B corresponds to the portion of the temperature rise in each device i due to the power dissipation of device 1. The voltagecontrolled voltage sources in subnetwork A each have unity gain and are used to couple the voltage drops from each subnetwork B of the other devices, back to device 1. For example, the value of the voltage source E 12 is equivalently E 12 = AT 12 (t), where Z C12 is part of subnetwork B of device 2. Therefore, the voltage generated at the terminal of subnetwork A corresponds to the EOT of device 1, and is given by the following expression T DEV1 (t) = AT 1 (t) + AT 12 (t) + "+AT ln (t) + T amb . (3.4) Similar expressions can be obtained for the EOT's of the other (n 1 ) devices in the circuit since they each have similar thermal networks. The thermal coupling model is demonstrated by simulating a fivefinger HBT using a version of SPICE 2G.6 modified to model selfheating [Zwe97]. The device characteristics are simulated with and without the thermal coupling between emitter fingers. Figure 3.3 shows the results of the electrothermal simulations. When accounting for the thermal coupling, the current collapse phenomenon commonly observed in HBT's can be simulated [Liu93, Sei93, Liu95b]. Figure 3.3b illustrates how the outer fingers shut down as the middle finger begins to carry all of the current. The importance of modeling the thermal coupling is established by the fact that the collapse phenomenon is not reproduced when the simulations only account for self
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85 4 6 CollectorEmitter Voltage, V CE (V) (a) 40 30 c
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86 heating. Multipleemitter devices provide just one application for the thermal coupling model. It can be used on a larger scale for simulating thermal interactions within circuits, and it can be used on a smaller scale. By dividing a single device (or each finger of a device) into multiple subcells, the thermal coupling model could be used to simulate the temperature distribution within a device and phenomena such as current constriction [Koe94]. 3.3 A Lumped Electrothermal Model for MultipleEmitter BJT/HBT's Used together with a compact device model of either a BJT or HBT, the multipleemitter thermal impedance model and the thermal coupling network form a complete electrothermal model suitable for DC, AC and transient device/circuit simulation. This type of electrothermal model is generally more efficient for circuit simulation than either finite difference or finite element techniques; however, it can be quite complex for devices with a large number of fingers and/or fingers with a large number of subcells. In such a case, simulating moderateto largesize circuits could become impractical. The complexity of the electrothermal device model can be reduced by using a lumped modeling methodology. The measurement technique described by Zweidinger et al., referred to in this work as basecurrent thermometry, can extract the thermal impedance of a bipolar transistor using the temperature dependence of the base current [Zwe96]. By applying this extraction technique to the simulation of the complete electrothermal device model, a more compact lumped electrothermal can be produced. The lumped model implicitly contains all the details
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87 of the thermal actions and interactions described by the complete electrothermal model, but with less complexity. To present a clear discussion of the lumped electrothermal model generation methodology, a few definitions and conventions will be established. Due to the thermal interactions between fingers in a multipleemitter device a lateral temperature gradient will exist across the device. Therefore, the current distribution among the fingers may not be uniform since the hotter fingers will carry a larger amount of current. As power dissipation increases, the lateral temperature gradient also increases and eventually the device will become unstable and enter either thermal runaway (BJT's) or current collapse (HBT's). Prior to the onset of thermal instability, the lateral thermal gradient is small and the current distribution among the fingers is approximately uniform. When the device reaches the point of thermal instability, the fingers no longer operate under similar bias conditions and the current no longer divides evenly among the fingers. Therefore, before a device becomes thermally unstable, it is defined to be in the uniform operating regime; and, once the device becomes unstable, it is defined to be in the nonuniform operating regime. In the uniform operating regime, the EOT of the device varies linearly with the power and the complete electrothermal model can be represented by a single lumped device model and lumped thermal impedance, Z THL . The circuit representation for the uniform lumped model is shown in Figure 3.4a; the emitter area of the lumped device model is equal to the total emitter area of the multipleemitter device. As a device becomes thermally unstable the cooler fingers begin to turn off, leaving the hottest finger to conduct all of the current; the temperature
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88 B Oco k Ed 'op 'THL V o l amb V (a) B 0oc V QlF k Qof k EO 10 p IF ami) V OI p OF ami) V J LOI J LIO V V (b) Figure 3.4 Circuit representations of the lumped multipleemitter BJT/HBT electrothermal model: a) For the uniform operating regime; b) for the nonuniform operating regime.
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89 power relation becomes nonlinear and the uniform lumped model will not accurately model the device characteristics. To model this shutdown mechanism, the nonuniform lumped model, which is shown in Figure 3.4b, uses two lumped device models and four lumped thermal impedances to represent the entire device. Device Q IF is used to represent the hottest emitter finger. In a device with an odd number of fingers, the hottest finger will be the middle finger. If a device has an even number of emitter fingers, due to process variation, the hottest finger will be one of the inner most fingers. For consistency, in either case the hottest finger will be referred to as the middle finger. The other device model, Q OF , represents the remaining outer emitter fingers. The emitter area of Q IF is equal to that of a single emitter finger and the emitter area of Q OF is equivalent to the sum of the emitter areas of the outer fingers. The lumped thermal impedances Z SI and Z s0 model the self impedances of the middle finger and the outer fingers, respectively. In the case of Z so , the impedance represents the effective temperature rise in the lumped outer fingers due only to their power dissipation. The lumped coupling impedance Z CIO models the temperature rise in the middle finger due to the power dissipation in the lumped outer fingers. The reciprocal coupling impedance Z COI , corresponds to the effective temperature rise in the lumped outer fingers due to the power generation of the middle finger. Thermally triggered instability in bipolar devices can lead to circuit failure and even catastrophic device failure. Typically, this region of operation is avoided in circuit design. Therefore, in most cases, the uniform lumped model should be appropriate for most applications. However, if the effects of thermal instability on
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90 device/circuit operation need to be investigated the nonuniform model should be used. 3.3.1 A Review of BaseCurrent Thermometry Basecurrent thermometry uses the base current as a thermometer to extract the thermal impedance of a bipolar transistor [Zwe96]. The technique was developed for measurementbased extraction but can be applied to the simulation of compact device models as long as the models' temperature dependences are physically valid. The first step of the procedure is to determine the dependence of the base current on temperature. The response of the base current to changes in temperature is represented by the fractional temperature coefficient, defined as 1 dI B T c F a B )^af(35) By biasing a device in the commonemitter configuration (avoiding impactionization), and separately varying the collector voltage and the ambient temperature, the thermal resistance of the device can be extracted Since the basecollector conductance is typically negligible, any changes in the base current during the measurements are due solely to the change in operating temperature. Therefore, once the selfheating effects are accounted for, the fractional temperature coefficient can be determined from the measured base current variations.
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91 The second step of the procedure is to extract the transient thermal impedance. The collector and base currents of the device are monitored for a step in the collector voltage. The transient change in temperature can be expressed as I R (t)I R (0) where I B is the median value of the base current for the transient. The temperature change is then normalized by the magnitude of the power step, giving the following equation for the thermal impedance Z TH (t) = ^T(37) 3.3.2 Generation of the Lumped Electrothermal Model The first step in the lumped model generation is to extract the temperature coefficient of the base current by performing DC SPICE simulations at different ambient temperatures. The .TEMP control card is used to set the ambient temperature; temperature steps between 4 and 10 degrees are sufficient, where a geometric mean can be used to average TC F (I R ) over temperature to correct for nonlinearities. The base voltage should be selected for the desired operating point and for each temperature setting, the collector voltage should be swept over a range in the forward active region. The range of collector voltages should be large enough to produce a linear increase in base current. Examples of the resulting base current characteristics are shown in Figure 3.5. The base and collector current values should
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92 350 300 < 5 250' c g rj 200 u a PQ 150 100 C38.0 a bQÂ— Â©T amb = 27 Â°C BÂ—eT amb = 3iÂ°c A Â— AT amb = 33 Â°C ^"7T amb = 35 Â°C ^ V V ^ A A A AjSsl ~~AB Ba be8.2 8.4 8.6 CollectorEmitter Voltage, V CE (V) (a) 8.8 B9.0 134.4 8.2 8.4 8.6 CollectorEmitter Voltage, V CE (V) (b) 8.8 9.0 Figure 3.5 Simulated base current versus collectoremitter voltage: a) For varying ambient temperatures; b) for T amb = 27 Â°C.
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93 be stored at each bias point and used to calculate TC F (I B ) . For the uniform model, this process should be performed once, using the net base and collector currents of the complete device. For the nonuniform model, the procedure should also performed just once. The temperature rise in the middle finger, corresponding to either Z SI or Z C10 , can be taken directly from the multipleemitter thermal impedance model, so an extraction is not necessary. Therefore, only the temperature coefficient of the lumped outer fingers should be needed. The coupling impedances from the middle finger to each of the outer fingers should be turned off and the net currents of only the lumped outer fingers are used to calculate TC F (I B ) . The second step of the procedure is to generate the transient thermal response. The transistor should be set in the commonemitter configuration with the base voltage set to the value used to extract TC F (I B ). The collector voltage should be stepped between two bias points in the forwardactive region. The combination of the selected base voltage and collector voltage stepsize should set the current level such that a significant base current response results from the step in power. The risetime of the voltage step should be faster than the shortest expected thermal time constant and the step length should be long enough to allow the current response to reach steadystate. The base current should be recorded during the transient as well as the collector current values at the start and end of the step. Figure 3.6a shows an example of the transient base current response. Using (3.6) and the TC F (I B ) from the first step, the transient base current response can be converted into the transient temperature response. The magnitude of the power step can then used to normalize the temperature response, resulting in the transient thermal impedance; an example
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94
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95 is shown in Figure 3.6b. For the uniform lumped model, this procedure should be performed once, using the net transient base current response to calculate the lumped thermal impedance, Z THL . For the nonuniform lumped model, the procedure should only be performed for the extraction of Z so and Z COI from the net base current of the lumped outer fingers. When extracting Z so , the coupling impedances from the middle finger to the outer fingers should be turned off. The calculated temperature response should be normalized by the power dissipated in the lumped outer fingers. When extracting Z COI , the self impedances and the coupling impedances between each of the outer fingers should be turned off. The calculated temperature response should be normalized by the power dissipated in the middle finger. The self impedance Z SI in the lumped model corresponds to the selfimpedance of a single finger, which can be calculated directly using the multipleemitter thermal impedance model. The lumped coupling impedance Z CIO can also be calculated directly from the multipleemitter thermal impedance model; for a device with an odd number of fingers (nl)/2 i = 1 and for a device with an even number of fingers Z cio (n _ 1} (n2)/2 Zc(n/2) + 2 JL ^Ci i = 1 (3.9) where n is the total number of emitter fingers in the device.
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96 3.4 Verification of the Lumped Electrothermal Model To test the accuracy of the lumped electrothermal models, they are compared to the full electrothermal models using DC, AC and transient SPICE simulations. The following simulations of homojunction bipolar transistors use the QBBJT model in a modified version of MMSPICE [Jeo89, Lee96]. The HBT simulations were performed using a modified version of SPICE 2G.6 [Zwe97]. Figure 3.7 shows the simulated DC current characteristics for a tenfinger BJT. The device remains in the uniform operation regime for the simulated biases, and the lumped models produce nearly identical results. The discrepancies between the lumped and full electrothermal models are the greatest when the device is biased with a constant base current, in which case the error is less than 3%. When the device is biased with a fixed base voltage, the error between the lumped models and the full electrothermal models is no greater than 0.5%. Figure 3.8 shows the simulated DC current characteristics for a fivefinger HBT. When the device is biased with a fixed base voltage, it remains in the uniform operation regime and the results are similar to those for the homojunction bipolar device. Both lumped models produce similar results and match the full electrothermal model to within 3% error. However, when the device is biased with a constant base current, it becomes thermally unstable and goes into current collapse. Under these operating conditions, the outer fingers shut down, leaving the middle finger to conduct all the current. The uniform lumped model does not show the collapse phenomenon which results in a 17% error at the highest bias point. The nonuniform lumped model, however, does a good job of representing the full electrothermal model, producing no more than 2% error.
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97 10 9 < 8 5 7 u 3 6 c t 5 3 u o o u o U 4 3 2 1 OFull Electrothermal Model Â• Uniform Lumped Model Nonuniform Lumped Model e e e e e e e e e2 3 CollectorEmitter Voltage, V CE (V) (a) 2 3 CollectorEmitter Voltage, V CE (V) (b) Figure 3.7 Simulated DC current characteristics for a tenfinger BJT with A E = 20 x 1.6 im 2 for each emitter finger: a) The collector current as a function of collector emitter voltage for V BE = 0.75, 0.775 and 0.80 V; b) the collector current as a function of collector emitter voltage for I B = 10, 20 and 30 iA.
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98 2.5 2.0 u
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99 The smallsignal and transient performance of the lumped models were tested by simulating a cascode amplifier composed of two fivefinger BJT's. The results of the simulations are shown in Figure 3.9. The lumped models produce almost identical results (the curves appear on top of each other) and agree closely with the full electrothermal model. The error in the smallsignal gain is less than 1% and is due to errors in the DC operating point. Errors in the magnitude of the transient output waveform are less than 1%. For both the smallsignal and transient simulations, the lumped models correctly reflect the frequencyand timedomain responses. The lumped models match the unitygain frequency and phase response to within 4% of the full electrothermal model. The benefit of the lumped models is that they have fewer components and less complexity than the full electrothermal model. The reduction in complexity results in models that are more efficient to simulate, at the cost of some accuracy. One portion of the increased simulation time of the full electrothermal model is due directly to the added components used for the thermal model. The other part is due to the increase in the number of iterations required to reach convergence in the presence of thermal feedback. Thus, the nonuniform lumped model does not offer as much of a speed enhancement over the full electrothermal model as the uniform lumped model. The total job times for simulations shown in this section (performed on a SPARCstation 5) are given in Table 3.1.
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100 200 c >" w 3 O > 150 o o o o o o c "3 O u bo a 4Â» "o > I 100 50 10 L 10.6 3.6 2.6 o o o OFull Electrothermal Model Â— Uniform Lumped Model Â— Nonuniform Lumped Model 10^ 10 4 10Â° Frequency (Hz) (a) 10 10 12 OFull Electrothermal Model Uniform Lumped Model Â— Nonuniform Lumped Model 100 200 Time (nanosec) (b) 300 Figure 3.9 Smallsignal and transient simulations of a cascode amplifier using fivefinger BJT's with A E = 20 x 1.6 uim 2 for each emitter finger: a) Smallsignal voltage gain; b) the output voltage resulting from a 40 mV peaktopeak sinewave input at 10 MHz.
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101 Table 3.1 Total simulation time
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102 multipleemitter device model was reduced by extracting a lumped thermal response. In most cases, a multipleemitter device can be represented by a single compact device model and a lumped thermal impedance. The lumped model offers a significant speed increase over the full electrothermal model, resulting in more efficient circuit simulations.
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CHAPTER 4 A THREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR VERTICAL BIPOLAR TRANSISTORS FABRICATED WITH FULL DIELECTRIC ISOLATION 4.1 Introduction Bipolar junction transistors fabricated using full dielectric isolation (DIBJT's) offer many advantages over those fabricated with junction isolation in bulk wafer technologies. The parasitic capacitances and leakage currents from the collector to the substrate and from the collector to the junctionisolation implant are reduced with full dielectric isolation, which enhances device speed [Dav92]. The area taken up by the lateral dielectric isolation is typically smaller than the area of the diffused junctionisolation implant; therefore, full dielectric isolation is a means to increase the transistor packing density [Jer93]. Finally, full dielectric isolation also negates latchup, and improves radiation hardness [Gan92]. Full dielectric isolation of vertical BJT's can be achieved by using silicononinsulator (SOI) substrates with trench isolation. Figure 4.1 shows a diagram of a typical npn DIBJT. Direct wafer bonding (DWB) has become a common way to fabricate SOI substrates for bipolar technologies since it produces highquality, defectfree SOI films [Nis91, Dav92, Fei92, Jer93, Nak95]. The DWB technique thermally bonds one semiconductor wafer to the oxidized surface of another wafer. One wafer serves as the substrate and the other wafer is used for the actual device 103
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104 Base Collector O Buried Oxide Substrate Figure 4.1 Crosssection of a typical bipolar transistor fabricated with full dielectric isolation (DIBJT).
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105 fabrication. The oxide layer interposed between the two wafers becomes the buried isolation layer and is typically 0.4 to 2.0 (im thick [Dav92, Fei92, Nak95]. The devicefabrication wafer is thinned using chemical/mechanical polishing (CMP). One disadvantage of DWB is that the resulting silicon film can have large variation in thickness [Nis91]. Once the SOI wafer is prepared, the BJT fabrication process can follow the typical steps used for bulk, trenchisolated devices. The backfill for the trench isolation is usually formed with chemical vapor deposition (CVD) oxide (0.1 to 1 .0 urn thick) or a combination of CVD oxide and polysilicon (0.5 to 2.0 p:m thick) [Nis91, Fei92, Nak95]. The device region enclosed by the trench isolation is referred to as the "tub," and the region surrounding the trenches is referred to as the "exterior silicon." Typical tub thicknesses range from 1.5 to 10 Jim [Nis91, Fei92, Nak95]. A major disadvantage of full dielectric isolation is an increase in selfheating. The oxide used in the trench and buried isolation has a low thermal conductivity and impedes the flow of heat away from the device, resulting in higher operating temperatures. The thermal resistance of a DIBJT can be three times larger than that of its bulk counterpart [Gan92]. Previous methods for determining the thermal resistance of DIBJT's have relied on measurementbased extraction or complex numerical techniques such as finiteelement solutions [Nis91, Gan92]. Both of these approaches have been limited to steadystate operation and do not provide insight into the dynamic variation of temperature. Furthermore, neither approach is practical for use in circuit simulation: temperature measurements are complicated and are not predictive; finiteelement solutions are predictive but can require large amounts of computing time.
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106 This chapter details the derivation of a physicsbased model for the dynamic thermal impedance of DIBJT's operating in the forward active region. The effects of interconnect metallization on the thermal impedance are then investigated. The model is compared to threedimensional finiteelement simulations and measurements for verification. The model derivation is then simplified for the limiting case of steadystate heat conduction, resulting in a single closedform equation for the thermal resistance of DIBJT's. The limitations of the thermal resistance model are shown with comparisons to measurements and to the full thermal impedance model. 4.2 Derivation of the DIBJT Thermal Impedance Model For the derivation of the DIBJT thermal impedance model, the silicon tub is represented by a homogeneous finite medium with an adiabatic top surface (no heat transfer perpendicular to the surface). The interface between the buried oxide and the substrate is assumed to be at a uniform temperature, T . Figure 4.2 shows a threedimensional crosssection of the simplified device geometry assumed for the model derivation. The definitions of the model parameters are given in Table 4.1. The imbedded heat source represents the base/collector spacecharge region (SCR), and is modeled by a rectangular volume. The thickness of the base/collector SCR can be estimated using the depletion approximation as given in Chapter Two. The heat generated in this region is assumed to be due to uniform power dissipation. As verified for the bulk BJT thermal impedance model, this assumption is reasonable for
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107 'box V IK 'trox 'poly Figure 4.2 Crosssection of the simplified device geometry used to define the solution domain for the DIBJT thermal impedance model. The silicon tub is represented by a homogeneous finite medium with an adiabatic top surface. The model parameters are defined in Table 4.1.
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108 Table 4.1 DIBJT thermal impedance model parameters Parameter
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109 the forwardactive region before the onset of highcurrent effects. The heat source is displaced beneath the surface of the wafer by a distance assumed to be the depth of the base/collector junction. Any encroachment of the base/collector SCR into the base region is neglected since the base typically has a higher doping than the epi collector. The width and length of the silicon tub are assumed to scale directly with the width and length of the emitter stripe by the relations W tub = W + C W1+ C W2 (4.1) and L tu b = L + C L , (4.2) where C W1 , C w7 and C L are constants that depend on the fabrication process. Since the tub material is assumed to be homogeneous, the model neglects the effects of the LOCOS isolation that is used to cap the trench structure and to separate the base and emitter from the collector contact implant. This assumption is reasonable since the LOCOS is typically shallow semirecessed LOCOS. The adiabatic boundary condition at the top surface of the device dictates that conduction through the interconnects and conduction/convection from the surface are neglected. This assumption is valid for the device regions that lie under thick silicon dioxide, since the thermal conductance from the device to the overlying oxide is approximately two to three orders of magnitude smaller than the devicetosubstrate conductance. The effects of conduction via the interconnect metallization are examined later in the chapter.
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110 The temperature rise at any point within the tub can be described by the nonhomogeneous threedimensional heat conduction equation V2 AT tub (x,y,z,t) + I^i) = Â± ^,^0 k sl Â«si dt (4.3) and the following boundary conditions 3AT tub (x, y, z, t) H tr (t)AT tub (x,y,z,t) = x = (4.4) r ^AT tub (x, y, z, t) H tr (t)AT tub (x,y,z,t)l = x = L,, (4.5) f aAT tub (x, y, z, t) dy H tr (t)AT tub (x,y,z,t)] = y = (4.6) p 3AT tub (x,y,z,t) 3y H tr (t)AT tub (x, y, z, t) = y = w lub (4.7) aAT tub (x, y, z, t) 3z + H b0X (t)AT tub (x,y,z,t) = z = (4.8) 3AT tub (x, y, z, t) = o z = d lub (4.9) where AT tub is the temperature rise above the local reference temperature (AT tub = T tub T ) , g is the internal energy generation density, k is thermal
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Ill conductivity, a is thermal diffusivity (a = k/(p Â• c ) where p is density and c is specific heat) and t is time. Typical values for the material properties are given in Table 4.2. The terms H tr (t) and H box (t) are normalized heattransfer coefficients that model the timedependent heat flow through the trench and buried oxide, respectively. Equations (4.3) through (4.9) assume that the thermal conductivity is independent of temperature and position. For the tub material, the variation of k with temperature can be accounted for with the Kirchoff transformation detailed in Chapter Eight. However, the thermal impedance of a DIBJT is mainly determined by the isolation structures, and the thermal conductivity of silicon dioxide varies by less than 13% from 303 to 433 K [Goo95]. Also, as shown in Chapter Two, the thermal conductivity remains approximately constant over a wide impurity doping range, and any spatial dependence of the thermal conductivity can be neglected. With the initial temperature rise of the device specified as AT tub (x,y,z,0) = 0, (4.10) the solution to (4.3) can be expressed in the form t YT tub (x, y, z, t) = p J dt'JG(x, y, z, tx', y\ z, t')g(x', y', z', t')dv' (4. 1 1 ) SI f = o v where
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112 Table 4.2 Material Properties Property
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113 G(x, y, z, tx', y', z, t') = I exp[a si P^(tt')]^i^X(P m ,x)X(P m ,x') Iexp[a s ^(tt')]^Y( Yn) y)Y(y n ,y') S exp[a si Ti p (t 1')]^Â— ^Z(Ti p> z)Z(Ti p , z') r> = 1 (4.12) is the Green's function for the given boundaryvalue problem [Ozi93]. The expressions for the eigenfunctions are determined by the boundary conditions for each direction. For the xand y directions X((3 m ,x) = P m cos(P m x) + H tr (t)sin(P m x) (4.13) Y(Y n , x) = y n cos(Y n x) + H tr (t) Â• sin(Y n x) (4.14) N(P m ) = 2[W tub {p^ + H t 2 r (t)} + 2H tr (t)r' (4.15) = 2[L tub {Yn + Hf r (t)} + 2H tr (t)r' N(Y n ) (4.16) where the eigenvalues are determined by the positive roots of the following transcendental equations , ,R T . 2 Pn,H tr (t) tan (P m L .ub) = ~ 2 Â— (4.17)
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14 2y n H tr (t) tan(Y n W tub )= 2 " (4.18) For the z direction Z(r>,z) = cos[Ti p (d tub z)] (4.19) 2[Tl' + Hj 0X (t)] N( V d tub [TiJ + Hj ox (t)] + H box (t) (4.20) where the eigenvalues are determined by the positive roots of the following transcendental equation Tl p tan(Ti p d tub ) = H box (t). (4.21) Equation (4.12) physically represents the temperature rise at any point (x, y, z) in the tub at time t, due to an instantaneous point source at point (x', y', z) at time t'. To account for the heatgeneration volume (V = WLH), (4.12) is integrated over the base/collector SCR. Assuming a unit step increase in power dissipation at time t = and expressing the temperature rise in the tub as AT tub (t) = Z TH (t) P (4.22) yields the transient thermal impedance
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115 Z TH (x, y, z, t) = Â— L_f p c VJ ,2. n 1 I expIa si P;t] i ^5 X(P m ,x)X(P in ) X eX Pta siY^N(Â— j Y (Yn'y) Y (Yn) S ex p[a s^p t ]j^n Z(T1 P' z)Z(r p ) Lp=l N(Ti p ) dt (4.23) where X(p_) = 2sin P m L" cos (U^ C, +L + H tr (t) sin P, C L + L (4.24) Y(y n ) = 2sin rr n wcos Yn C W1 + W H tr (t) . + sin Y n YÂ„C W l + ~2 (4.25) Z(Ti p ) = ^{sin[r p (D + H)]sin[Ti p D]}. Id (4.26) To represent the temperature rise in the device by a single effective value, (4.23) should be evaluated at a single point. The coordinates for surface corner of the emitter, (x = C L /2, y = C W1 , z = d tub ), are substituted into (4.13), (4.14) and (4.19) to keep the model consistent with the bulk BJT thermal impedance model. As shown later in the chapter, the model evaluated at those coordinates agrees well with measured values of the steadystate thermal resistance. Most of the parameters for the DIBJT thermal impedance model are fixed by the geometry of the device structure. However, the parameter H depends on the
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116 electrical bias of the device and can change with operating conditions. As shown in Chapter Two, the base/collector SCR thickness, and hence the thermal impedance model, depends only moderately on the bias of the base/collector junction. For the DIBJT thermal impedance model, this dependence is weaker than that for the bulk BJT model since the dielectric isolation primarily determines the thermal impedance. The variation in the predicted thermal resistance of a DIBJT due to changes in H is approximately onehalf to onethird that of a bulk BJT. The variation will increase as the thickness of the dielectric isolation is decreased or the tub scaling constants are increased; however, for most practical DIBJT structures, the dependence of the thermal impedance on bias can be neglected. The DIBJT thermal impedance model can be extended to account for BJT's with multiple emitter fingers by integrating (4.12) over each base/collector SCR. Using an analysis similar to that in Chapter Two for bulk MEBJT's, expressions for the self and coupling impedances can be derived. 4.2.1 Derivation of the BuriedOxide HeatTransfer Coefficient The normalized heattransfer coefficient of the buried oxide, H box (t) , describes the timedependent heat conduction through the buried oxide to the substrate. The heat flux through the buried oxide is assumed to be predominantly onedimensional (1D). This assumption is valid for most of the tub area (A tub = W tub L tub ) but is questionable at the edges of the tub, where the heat flows out laterally under the trench. However, analogous to field fringing effects in parallelplate capacitors, the proportion of lateral heat flow becomes smaller as the
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117 tub area becomes larger. Figure 4.3 shows the results of ANSYS simulations of the heat flow through the buried oxide. The data corresponds to the z component of the heat flux vector in the buried oxide, normalized by the heat flux vector magnitude (referred to as the "flux ratio"). The plots clearly show that the heat flux in the buried oxide is predominantly 1D, even at the interface between the trench and the buried oxide. The temperature rise in the buried oxide, AT 0X = T ox T , can be described by the heat conduction equation a 2AT box = i 3AT box (427) dz 2 ' Â« ox 3t The following boundary conditions are imposed at the interface between the tub and the buried oxide 3AT 0X dAT tub k ^ = k ^ (4 28) AT 0X = AT tub (4.29) and at the interface between the buried oxide and the substrate AT 0X = 0. (4.30) Using the variable substitution
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118 Tub Area, W tub L tub (iim 2 ) (b) Figure 4.3 The ratio of the z component of the heat flux vector to the magnitude of the total heat flux vector in the buried oxide with d box = 1 u.m. L = 2 im and W = 0.5 im: a) For C W] = C W2 = C L /2 = 5 im; b) the portion of the tub area where the flux ratio is unity (signifying complete 1D heat flow) for C W1 = C w2 = C L /2 = 3, 4, and 5 (im.
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119 S V^T 1 ' (4.31) (4.27) is transformed into the following ordinary differential equation d AT ox  ^dAT c < 2 dÂ£ = 0. (4.32) Equation (4.32) has a general solution of the form AT ox = C l erf ^) +C 2 (4.33; where c, and c 2 are arbitrary constants. The equation that describes the flux at the interface between the tub and the buried oxide can be derived by substituting (4.31) into (4.33) and then applying the boundary conditions given by (4.28) through (4.30). The resulting expression 3AT tub kox^Ttub S1 dz JÂ™^> erf ( d box  (4.34) when rearranged into the form given by (4.8), yields the normalized heattransfer coefficient for the buried oxide Hox(t) = k siVÂ™W erf box M fiv^hj (4.35)
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120 4.2.2 Derivation of the Trench HeatTransfer Coefficient The normalized heattransfer coefficient of the trench isolation, H tr (t) , describes the timedependent heat conduction through the trench structure and exterior silicon to the substrate. To simplify the analysis, the thickness of the trench is assumed to be uniform along the z direction and the composite trench structure is represented by a single material with the lumped thermal properties [Man90] H k k , u tr*oxV,1y . 36 K tr " oh k +d k ( ' zu trox K poly + u poly K ox ^trPtr c ptr 2d trox p ox c pox + d poly p poly c ppoly (4.37) d tr = 2d trox + d poly (4.38) k tr Ptr C ptr The heat flux through the trench is assumed to be predominantly onedimensional ( 1D). This assumption is valid for most of the trench area ( A tr = W tub d tub or L tub d tub ), but is questionable at the corners of the trench structure and at the edges between the trench walls and the buried oxide. Figure 4.4 shows the results of ANSYS simulations of the heat flow through the trench. The data corresponds to either the x or the y component of the heat flux vector in the trench which is normalized by the heat flux vector magnitude (referred to as the "flux ratio"). The plots clearly show
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121 ZDirection (um XDirection (um) Figure 4.4 The ratio of the y component of the heat flux vector to the magnitude of the total heat flux vector in the trench for half of the trench wall. The device parameters are L = 2 u.m, C L = 10 im, d [rox = 0.25 im and poly = 1.6 u.m.
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122 that the heat flux in the trench is predominantly 1D, even at the corners of the trench and at the interface between the trench and the buried oxide. The temperature rise in the trench, AT tr = T tr T , can be described by the heat conduction equation 3 2 AT, r i 3AT tr 5?= ^,ir Â• < 4 40 ' where n is either the xor y direction. The following boundary conditions are imposed at the interface between the tub and the trench dAT tr 3AT fnh A T tr = AT tub (4.42) and at the interface between the trench and the exterior silicon 3AT tr 3AT sj AT .r = ^T sl . (4.44) The boundary conditions given by (4.43) and (4.44) require a solution for the temperature rise in the exterior silicon, AT si = T si T . The temperature in the exterior silicon can be derived by assuming that the heat flow is primarily in the directions normal to the trench walls. Therefore, the temperature rise in the exterior
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123 silicon is assumed to be onedimensional. The validity of such an assumption can be evaluated using the Biot number, which corresponds to the ratio of the internal and external thermal resistances of a given object [Ozi93]. If the Biot number for an object is much less than unity, then it can be approximated by a onedimensional thermal medium. The vertical Biot number for the exterior silicon is B Vsi = (k ox d tub )/(k si d box ), so that for d tub Â« 100 d box the vertical temperature gradient can be neglected. The extent of the temperature gradients in the directions parallel to the trench walls is also investigated by simulating the heat flux in the exterior silicon at the trench/exterior silicon interface. Figure 4.5 shows the results of one such ANSYS simulation. For most of the trench area, the heat flux is primarily perpendicular to the trench walls. However, the onedimensional assumption does break down around the corners of the trench where the heat flow becomes more twodimensional. Therefore, the onedimensional model will tend to slightly under predict the heat transfer through the trench. The exterior silicon can be divided into four regions surrounding the trench; each region is modeled as a onedimensional cooling fin. To approximately account for the lateral spread of heat around the corners of the trench, each cooling fin is assumed to have an increasing crosssectional area. The temperature rise in the each exterior silicon cooling fin can be described by a 2 AT si i 3AT si 2 i 3AT S1 + 7 Â„ . S m'AT,: = *2. (4.45) dn 2 (n + C n ) 3n S1 s > a si 9t
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124 ZDirection (um) XDirection (um) Figure 4.5 The ratio of the y component of the heat flux vector to the magnitude of the total heat flux vector in the exterior silicon at the trench/exterior silicon interface. The device parameters are L = 2 im, C L = 10 J.m, d trox = Â° 25 ^ m and d poly = 16 ^ m 
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125 The constant C n is (L tub + 2d tr )/(2tan0 L ) for the x direction and (W tub + 2d tr )/(2tan8 w ) for the y direction, where W and G L are the thermal spreading angles for the cooling fins which are assumed to be 45Â° [Hir93]. The third term on the lefthand side of (4.45) accounts for heat lost from the exterior silicon due to conduction through the buried oxide, where d tub m si V H ox(t) (4.46) is the characteristic thermal length in the exterior silicon. Equation (4.45) does not have a simple closedform solution. However, a solution to the steadystate form of (4.45) exists and, by using the timedependent characteristic thermal length, can be used to approximate the temperature rise in the exterior silicon as AT S] = c 1 K [m sj (t)(n + C n )], (4.47) where c, is an arbitrary constant and K ; is the modified Bessel function of the second kind of order i . The equation that describes the flux at the interface between the tub and the trench is derived by solving (4.40) using (4.31), (4.41) through (4.44), and (4.47). The resulting solution, when arranged into the form given by (4.4), yields the normalized heattransfer coefficient for the trench
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126 H, r (t) = k tr m si K,(m si C n ) . (4.48) k si m siVÂ™V ' erf ( d tr ^ V 4 ^ K l( m si C n) + k tr eX P v 4Â« tr t y ^ ( m si C n) 4.2.3 Effects of Interconnect Metallization on the Thermal Impedance For the derivation of the DIBJT thermal impedance model, the surface of the device is assumed to be adiabatic, and therefore conduction through the interconnect metallization is neglected. Since the metallization typically has a high thermal conductivity, it is possible that the heat conduction via the interconnects significantly influences the thermal impedance. Therefore, the validity of such an assumption should be investigated. Based on the finiteelement (FE) simulations performed for bulk BJT's (Chapter Two), the heat conduction through base and collector interconnects is typically negligible and only the emitter interconnect is assumed to affect the thermal response of the device. To determine the extent of the effect of the emitter interconnect on the thermal impedance, both steadystate and transient threedimensional (3D) FE simulations of a DIBJT structure were performed using ANSYS. The FE model represented a simplified device structure and was constructed using similar assumptions and boundary conditions to those detailed in Chapter Two. Figure 4.6a shows the FE model used for the thermal simulations. The simulations were carried out with and without the emitter interconnect present, while independently varying each structure parameter of the FE device model.
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127 (a) 30 ^
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128 The results of the steadystate FE simulations are shown in Figure 4.6b. As with the bulk BJT's simulated in Chapter Two, the emitter interconnect enhances the heat flow away from the active device area, resulting in lower thermal resistance values. As was the case with the bulk BJT FE model simulated in Chapter Two, the effectiveness of the interconnect as a thermal conductance path increases as its crosssectional area increases or as the interconnect is effectively moved closer to the heat source. However, the influence of the emitter interconnect on the thermal resistance is more significant for the DIBJT's than for the bulk BJT's. This effect is due to the lower thermal conductance to the substrate of DIBJT's as compared to the bulk devices. Therefore, the conductance through the emitter interconnect becomes a larger component of the total thermal conductance of the device. This trend is illustrated by the data in Figure 4.6b, which shows that as the conductance to the substrate is increased by enlarging the tub or thinning the isolation oxides, the effect of the emitter interconnect on the thermal resistance is reduced. Since the effect of the emitter interconnect is increased due to the dielectric isolation, it is reasonable to suggest that the effects of the base and collector interconnects on the thermal resistance will also increase. Therefore, the assumption that the base and collector metallization is negligible becomes questionable. However, the increase in the effects of the base and collector interconnects should not be any greater than that for the emitter interconnect. Consequently, even for a twofold increase in the influence of the base and collector metallization in a bulk technology, the heat conduction through the base and collector interconnects will still be negligible.
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129 Transient thermal simulations were performed to examine the effect of the emitter interconnect on the dynamic temperature response. ANSYS was used to simulate the structure in Figure 4.6a for a step increase in power dissipation, both with and without the emitter interconnect in contact with the device. Figure 4.7 shows the results of the transient FE simulations. The observed trend in the transient temperature rise is similar to that for the bulk bipolar devices in Chapter Two. The additional heat capacity of the emitter metallization effectively slows the temperature rise in the device. The extent of the metallization's effect on the dynamic temperature response is directly related to the effective volume of the interconnect structure, and will be more pronounced for large devices with substantial contact area. Therefore, the model that neglects the conduction through the interconnect by assuming an adiabatic surface will produce the quickest possible temperature rise. 4.2.4 A Model for the Thermal Impedance of the Emitter Interconnect As detailed in Chapter Two, the effect of the emitter interconnect on the thermal response can be modeled by an additional thermal impedance. This thermal impedance is derived by calculating both the thermal resistance and thermal capacitance of the emitter metallization. The emitter interconnect is represented by a onedimensional cooling fin, such that the thermal resistance can be expressed as R T Hmet = [kmetrnmetWmetdme.r 1 (4.49)
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130 U u c J^ 2 C3 Â£ sH O O With Emitter Interconnect O Without Emitter Interconnect 06 10 12 10 tfBB Â— eo 10"Â° 10 Time (sec) 6 If) 4 ioFigure 4.7 ANSYS simulations showing the effect of the emitter interconnect on the thermal impedance. The simulated FE device model used the nominal structure parameters listed in the caption of Figure 4.6.
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131 where in met k d /'"met^met met (4.50) is the characteristic thermal length in the interconnect and k ox k si met k si( d ox + d box) + k ox d tub (4.51) is the heattransfer coefficient from the interconnect to the substrate. The material properties for the emitter interconnect are given in Table 4.3. Table 4.3 Emitter interconnect* material properties Property
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132 Therefore, the transient thermal impedance of the emitter interconnect can be approximated as ZTHmetW = R TU me t[ l ~ ex p(; ^met (4.53) where x met = RTHmet^THmet The overa U thermal impedance of a bipolar device can now be represented by the parallel combination of two thermal impedances, such that effectively ZTHdev( S ) Â• Z THmet (s) ^THdev( s ) + ZxHmet( s ) Zth( s ) = ^ ,_. . J ,x . (454) where Z THdev (s) is determined from the transient thermal impedance given by (4.23). 4.3 Verification of the DIB JT Thermal Impedance Model To verify the thermal impedance model, threedimensional (3D) finiteelement (FE) simulations of a DIBJT were performed using ANSYS. The FE model represented a simplified device structure and was constructed using similar assumptions and boundary conditions to those detailed in Chapter Two. In addition, all interconnect metallization was neglected and the tub region was assumed to be composed of homogeneous silicon with the bulk properties given in Table 4.2. The FE simulations were evaluated at the surface corner of the emitter and compared to (4.23); the results are shown in Figure 4.8. The DIBJT thermal impedance model
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133 Figure 4.8 The transient thermal impedance simulated with ANSYS and calculated with the DIBJT model for d tub = 1.5 Jim, d box = 0.5 im, d trox = 0.13 fxm and d poly = 0.5 (im: a) L = 2 fim and W = 0.5 (im; b) L = 3 im and W = 0.7 j.m
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134 agrees closely, for both the transient and steadystate, with the 3D FE simulation results. The largest error, which is approximately 17%, occurs in steadystate and can be partially attributed to numerical error associated with limitations of the FE mesh. The model was also compared to measured thermal impedance data extracted by Zweidinger et al. using a basecurrent thermometry technique [Zwe96]. Figure 4.9, Figure 4. 10 and Figure 4. 1 1 compare the measured and simulated data for the transient thermal impedances of Harris UHF DIBJT's. The thermal impedance model does a good job of predicting the steadystate thermal resistance, with no more than 1 1% error between the model and the measurements. However, the model given by (4.23) tends to exaggerate the transient response. This discrepancy can be attributed to the model's neglect of the emitter interconnect metallization. Equation (4.23) predicts the quickest temperature response in the device since it does not account for the additional heat capacity of the metallization. However, when the thermal impedance of the emitter interconnect is accounted for, with 5 met = 100 (im extracted from the measurements, the model provides a more accurate representation of the transient temperature response. 4.4 Derivation of a Compact DIBJT Thermal Resistance Model For the limiting case of steadystate thermal conduction, the complexity of the DIBJT thermal impedance model can be reduced, resulting in a single closedform expression for the thermal resistance. The approach for the derivation of the thermal resistance model is adopted from the analysis by Goodson and Flik for SOI
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135 300 250 U o 200 tf o c
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136 200 U Â°^ 150 Â§ 100 5 o o I rt 0) 50 Ofi10" Measurement Â©Â©Model: Without Emitter Int [Â•}Â•Model: With Emitter Int. Qiiry. 150 U o X O o U On 100 E 50 E su H OS 10 9 Measurement Â©Â•OModel: Without Emitter Int. a Â— Model: With Emitter Int. ~QFigure 4.10 Measured and simulated data for the transient thermal impedance of Harris UHF DIBJT's with W = 3 im: a) L = 90 fim; b) L = 1 10 urn.
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137 100 75 U I u Â« 50 T3 U I  25 H Ofr 10" Measurement G>OModel: Without Emitter Int. BE3 Model: With Emitter Int. &Â• .Â©Â• =ei v3 100 & 75 (J g 50 a u I 03 JS 25 i Â— r  I I I I I I  'T T T I T I 0610' Measurement 0Â—0 Model: Without Emitter Int BÂ— Â€1 Model: With Emitter Int. ~e3 Figure 4.11 Measured and simulated data for the transient thermal impedance of Harris UHF DIBJT's with W = 3 urn: a) L = 170 urn; b) L = 210 urn.
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138 MOSFET's [Goo92]. The model represents a solitary DIBJT device with three parallel conductance paths that carry heat away from the tub. These heatflow paths are illustrated in Figure 4.12 and are modeled by a system of coupled onedimensional differential equations. The derivation of the thermal resistance model is divided into separate regions that correspond to the different thermal conductance paths. Different subscripts are used to denote the equations and variables that apply to the different regions; the subscripts tub, e and si refer to the tub region, emitter interconnect and exterior silicon region, respectively. Figure 4. 13 shows the simplified device structure that defines the geometry for the model derivation. The definitions of the model parameters are listed in Table 4.4. The defining assumption for the DIBJT thermal resistance model, and the main departure from the thermal impedance model, is that the entire tub is considered to be a heat source, with uniform power dissipation equal to the actual device power P, at a single uniform temperature, T tub . Since the thermal conductivity of the tub silicon is much greater than that of the insulating oxide, the thermal conductance of the tub is larger than that of the trenches or the buried oxide, and the thermal resistance of the device is mainly determined by the isolation structures. This assumption is supported by both ANSYS simulations and the MEDICI simulation in the work by Ganci et al. [Gan92]. Figure 4.14 shows the ANSYS results, which illustrate that the temperature gradient in the tub is smaller than the gradients across the isolation structures. However, the validity of this assumption declines as the dimensions of the tub, A tub = W tub L tub , become much greater than those of the active device, A dev = W Â• L, or the thickness of the insulating oxide layers (buried
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139 Tub temperature, T tub Q Along emitter interconnect Substrate temperature, T Figure 4.12 Illustration of the three parallel conductance paths for heat to travel from the device tub to the semiconductor substrate.
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140 V///////A Tub Buried Oxide Substrate 'tub 'box si K tub y S i o w (a) 'tub (b) T o *S1 'poly 'trox T W Â£ Figure 4. 1 3 The simplified device geometry used to define the solution domain for the DIBJT thermal resistance model. The model parameters are defined in Table 4.4: a) Crosssectional view; b) top view.
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141 Table 4.4 DIBJT thermal resistance model parameters Parameter
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142 Ydirection (urn Ydirection (um) Zdirection (um) (b) Figure 4. 14 ANSYS simulation results showing the temperature gradient in the tub and across the isolation structures: a) For A tub /A dev = 9; b) for Atut/Adev 1Â°
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143 or trench) is reduced. For such conditions, the conductance of the tub is reduced and the temperature gradients within the tub become more significant, so that the model will tend to underestimate the thermal resistance. The boundary conditions and the model parameters for the thermal resistance model, for the most part, are the same as those for the thermal impedance model. The interface between the buried oxide and the substrate is assumed to be at a uniform temperature T , and the device is assumed to cool solely through the substrate. The width and length of the tub region are assumed to scale directly with the width and length of the emitter stripe; one change from the thermal impedance model is that the scaling constants C W1 and C W2 have been lumped together so that W tub = W + C w . (4.55) The top surface of the device is considered adiabatic so that heat conduction through the overlying oxide layers is neglected. Based on the finiteelement simulations in Chapter Two, only the emitter interconnect is assumed to affect the thermal resistance. However, since the tub is assumed to be at a uniform temperature, the effects of the base and collector metallization can be incorporated using a similar analysis as shown below. The emitter interconnect is still treated as a onedimensional cooling fin. Therefore, the temperature rise along the interconnect can be described by the following differential equation
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144 a 2 AT e 2 e m e AT e = (4.56) 5x e and the boundary conditions AT e  =AT mb (4.57, ATI = 0, (4.58) where AT e (x e ) = T e (x e )T . The assumption that the temperature gradient in the emitter interconnect is primarily onedimensional was validated in Chapter Two. The width of the emitter interconnect is assumed to scale directly with the width of the emitter stripe W e = W + C e , (4.59) where C e depends on the fabrication process. The characteristic thermal length and the heattransfer coefficient for the interconnect are given by (4.50) and (4.51), respectively. The heat lost from the tub through the trench is governed by the steadystate heattransfer coefficient of the trench. The temperature gradient in the trench is assumed to be onedimensional and the exterior silicon is modeled by four onedimensional cooling fins where for steadystate, the characteristic thermal length is ksjdtub m s, V h ox (4.60)
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145 and the buriedoxide heattransfer coefficient is given by h ox = I ox (4.61) box The flux at the interface between the tub and the trench can be expressed as 3AT tr (4.62) Equation (4.62) can be solved for the heattransfer coefficient of the trench, h tr , using the steadystate form of (4.40), equations (4.41) through (4.44) and (4.47), resulting in k tr k S1 m S1 K l( m s, C n) "tr d tr k si m si K l( m s, C n) + k tr K o( m si C n) (4.63) The thermal conductance paths are coupled through the following power conservation equation 3AT " k e W e d e JW + hox W tubL t ub AT tub + 2 M,ub( W tub + L t ub)AT tub = P . (4.64) x =0 Equation (4.64) can be solved in the form AT tub = R TH P (4.65: resulting in the following expression for the thermal resistance
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146 r th = [k e W e d e m e + h 0X W tub L tub + 2h tr d tub (W tub y y + L tub Y x )] l (4.66) k si m s, K l rÂ™.i( W tub + 2d tr)2tan0 Yv w h tr K rm si (w tub + 2d tr )2tan0 w + k si m si K l r m si( W tub + 2d tr)2tan9 w (4.67) k si m si K l Tx = m si( L tub + 2d tr) 2tan0, htr^o r m si( L tub + 2d tr)2 tan 6, + k si m si K l m si( L tub + 2d tr> 2tan6, (4.68) The first term on the righthand side of (4.66) corresponds to the heat flow out through the emitter interconnect; the second term corresponds to the heat flow out through the buried oxide, and the third term corresponds to the heat flow out through the trench. 4.5 Verification of the DIBJT Thermal Resistance Model The accuracy of the thermal resistance model is tested with comparisons to measured steadystate thermal resistances and to the thermal impedance model; the results are shown in Figure 4.15. The thermal resistance model displays the proper trends with emitter length and tub scaling but as A tub /A dev increases, the accuracy of the model declines. For the DIBJT's with A tub /A dev > 30, the error between the thermal resistance model and the measured data is in excess of 20%. This trend is further illustrated by examining the thermal resistance of Harris
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147 400 U 300 1 200 CO "S3 JS H 100 O Measurement Zj H Model R TH Model 50 100 150 Emitter Length, L (J.m) 200 250 Figure 4.15 The steadystate thermal resistance extracted from measurements and calculated using both the thermal impedance and thermal resistance models; W = 3 im.
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148 "CoolingZone" DIBJT's. These devices were fabricated in larger tubs to reduce the thermal resistance. Table 4.5 shows a comparison of the measured and predicted thermal resistances for two "CoolingZone" devices. Table 4.5 Thermal resistance (Â°C/W) of Harris "CoolingZone" DIBJT's* L (Jim)
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149 4.6 Summary Due to the low thermal conductivity of the silicon dioxide used for the trench and buried oxide isolation, the thermal impedance of DIBJT's can be larger than that of their bulk counterparts. Therefore, selfheating effects can be enhanced and it is important to have a physical model that can predict the dynamic temperature rise. This chapter presented a thermal impedance model for DIBJT's. As with the bulk BJT/HBT's, the device interconnects can affect the thermal impedance. Neglecting the heat capacity of the emitter metallization results in a predicted thermal impedance that exaggerates the transient temperature response. Therefore, the emitter interconnect thermal impedance model, developed in Chapter Two, was utilized in this chapter. The DIBJT thermal impedance model was shown to agree reasonably well with both threedimensional finiteelement simulations and measurements. Finally, in the limit of steadysate heat conduction, the thermal impedance model was simplified to provide a single, closedform expression for the thermal resistance.
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CHAPTER 5 A THREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR BULK METALOXIDESEMICONDUCTOR FIELDEFFECT TRANSISTORS 5.1 Introduction Due to the development of complementary metaloxidesemiconductor technologies (CMOS), the bulk MOS fieldeffect transistor (MOSFET) has become the primary device used in semiconductor circuits. Figure 5.1 illustrates the crosssection of a typical bulk MOSFET structure. The MOSFET output current is not as strongly dependent on temperature as the current of bipolar transistors. The current's sensitivity to changes in operating temperature is mainly due to variations in the carrier mobility. A significant change in output current will be observed only for temperature variations of tens of degrees. Based on the thermal resistances of typical devices, such temperature excursions will only occur at high power levels. However, as MOSFET's are aggressively scaled towards tenthmicron channel lengths, thermal impedances are likely to increase and selfheating effects could be enhanced. Previous works in this area have provided methods for calculating the thermal impedance of bulk MOSFET's; however, these approaches were limited by inadequate derivations. In the work by Schutz et al. [Sch84], the twodimensional steadystate temperature distribution in a MOSFET was solved using a finite difference discretization of the heat conduction equation. The solution was 150
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51 Source psubstrate Figure 5.1 Crosssection of a typical bulk metaloxidesemiconductor fieldeffect transistor (MOSFET).
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152 calculated for a thin layer about the channel, where the boundary conditions were set by an effective onedimensional (1D) thermal resistance representing conduction in the substrate. The idea of the effective substrate thermal resistance was extended by Hirsch et al. [Hir93] into a quasithreedimensional analysis by coupling parallel 1D analyses. While the abovementioned techniques offer insight into steadystate heat conduction in bulk MOSFET's, they are not capable of determining the dynamic temperature response. A model for the dynamic thermal impedance of bulk MOSFET's was developed by Sharma and Ramanathan [Sha83]. However, this model was derived by neglecting the temperature variation along the width of the channel and the variation of the electric field along the length of the channel. Both of these assumptions can lead to significant errors in the predicted temperature rise within the channel region. The model derived in this chapter is based on an extension of the model developed by Sharma and Ramanathan [Sha83], and provides a closedform physical solution for the transient thermal impedance of bulk MOSFET's. The first part of this chapter details the derivation of the model and the improvements made to the existing work. The effects of LOCOS and shallow trench isolation and the drain, gate and source interconnects on the thermal impedance are then investigated using threedimensional finiteelement simulations. Finally, the accuracy of the thermal impedance model is evaluated using threedimensional finiteelement simulations and measurements.
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153 5.2 Derivation of the Bulk MOSFET Thermal Impedance Model For the derivation of the bulk MOSFET thermal impedance model, the silicon substrate is represented by a homogeneous semiinfinite halfplane with an adiabatic top surface (no heat transfer perpendicular to the surface). The back side of the substrate is assumed to be held at a constant temperature, T . Figure 5.2 illustrates the simplified device geometry assumed for the model derivation; the diagram focuses on the electrically active portion of the device around the drain, source and channel, which has a width W and length L. The heat source represents the power generated in the channel, which is assumed to be uniform along the channel width. Representing the substrate as a semiinfinite medium neglects the influence of the backside and the lateral edges of the wafer, as well as any LOCOS or trench isolation structures, on the thermal response of the device. The ramifications of neglecting the isolation structures are investigated later in the chapter. The surface of the wafer is assumed to be the only boundary that affects the thermal response of the device and it is considered to be adiabatic. With respect to the assumptions concerning the backside and lateral edges of the substrate, the bulk MOSFET model is identical to the bulk BJT model and the validation in Chapter Two applies. Assuming that the surface of the device is adiabatic implies that conduction through the source, gate and drain interconnects and conduction through overlying oxide layers are neglected. As shown in Chapter Two, the thermal conductance from the device through the overlying oxide is approximately two to three orders of
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154 (dT/dz) = Figure 5.2 The simplified device geometry used to define the solution domain for the bulk, MOSFET thermal impedance model. The substrate is represented by a semiinfinite halfplane with an adiabatic surface (the dashed lines). Heat is generated due to the power dissipation in the channel, which has a width W and length L.
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155 magnitude smaller than the devicetosubstrate conductance. Therefore, neglecting thermal energy transport from the field regions (the regions covered with thick oxide layers) of the device is reasonable. However, the device interconnects can have high thermal conductivities, and can provide effective paths for heat flow from the portions of the device they contact. The consequences of neglecting the interconnects are investigated later in the chapter. The heat source that represents the power dissipation in the channel depends on the region of operation and is considered to be a superposition of two individual heat sources. One source models the power dissipation in the fielddependentvelocity portion of the channel (referred to as the linear source). The other heat source models the power dissipation in the portion of the channel where the carrier velocity is saturated (referred to as the saturated source). The total temperature rise in the device can be expressed as a sum of the individual components due to the separate heat sources, and is given by AT(t) = Z THss (t)P ss + Z THls (t)P ls , (5.1) where Z THss (t) and Z THls (t) are the transient thermal impedances of the saturated and linear sources, respectively. When a MOSFET is operating in the saturation region, the power dissipation associated with the saturated source is approximately PÂ„ = (V fU V fk JI ds , (5.2) and for the linear source
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156 P ls = V dss I ds , (5.3) where V dss is the drainsource voltage at the onset of the saturation region. For a device operating in the linear region, the effect of the saturated source is removed P ss = (5.4) and the linear source accounts for the total power dissipation p is = V ds I ds(5.5) The original model derived by Sharma and Ramanathan assumed that the temperature gradient along the width of a MOSFET was negligible [Sha83]. However, ANSYS simulations of a MOSFET structure have shown that the temperature variations across the width of a device, for aspect ratios (W/L) greater than ten, can be in excess of 10% to 17%. Therefore, the twodimensional analysis of the original model is extended into three dimensions. The temperature rise at any point within the device can be described by the nonhomogeneous threedimensional heat conduction equation V2AT(x, y, z, t) + g (x 'y> Z ' C) = l^T(x,y,z,t) k a dt and the following boundary conditions AT(Â±oo, y , z, t) = (5.7) AT(x, Â±oo, z , t) = (5.8)
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157 3AT(x, y, z, t) dz = (5.9) z = AT(x,y,oo,t) = 0, (5.10) where AT is the temperature rise above the local ambient (AT = TT ), g is the internal energy generation density, k is the thermal conductivity, a is the thermal diffusivity (a = k/(p Â• c ) where p is the density and c is the specific heat) and t is time. Typical values for the material properties of bulk silicon are given in Table 5.1. Table 5.1 Material properties of silicon Property
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158 accounted for using the Kirchoff transformation described in Chapter Eight. Neglecting the spatial dependence of the thermal conductivity implies that the effect of dopant atoms is ignored. In the highly doped source and drain regions, the thermal conductivity can be significantly lower than the bulk value given in Table 5.1. However, these regions are relatively small and the majority of the device substrate is relatively lowdoped; therefore, as shown in Chapter Two, the average thermal conductivity of the substrate will not differ greatly from the intrinsic value. With the initial thermal conditions in the device specified as AT(x,y,z,0) = 0, (5.11) the solution to (5.6) can be expressed in the form AT(x,y, z,t) = ^ J dt'G(x,y,z,tx',y',z',t')g(x',y',z',t')dv' (5.12) t' = o where G(x, y, z, tx', y', z', t') = 1 8[7COC(tt')] jexp 3/2 exp (zz) _4a(tt'). ~(xx') 2 4a(tt')_ + exp exp (yy) _4a(tt ) (z + z) 4oc(tt'). (5.13) is the Green's function for the given boundaryvalue problem [Ozi93]. Equation (5.13) physically represents the temperature at point (x, y, z) at time t, due to an instantaneous point source, g' (W s), of unit strength at point (x', y', z') at time t' .
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159 To account for a finite substrate thickness, (5.13) can be modified in a similar fashion as detailed in Chapter Two for the bulk bipolar model. The resulting expression for the Green's function is G(x, y, z, tx', y', z', t') = 1
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160 rectangular sheet source of length L, and the saturated source is modeled by a line source at the drain/channel junction. To produce a physically consistent model, a more rigorous analysis was attempted that models the saturated source as a rectangular sheet with a length equal to that of the velocitysaturated portion of the channel. The length of the saturated portion of the channel can be derived using the analysis by Green [Gre93], giving L L e = l c Â• In ^ c {( V d S V dss ) + J(V ds V dss ) 2 + 4(^ 1 ^ (5.16) where l c is the characteristic length of the surface potential. While (5.16) provides a more physical characterization for the length of the saturated source, two problems are associated with its implementation. First, equation (5.16) is strongly biasdependent. Thus, the thermal impedance of the saturated source would need to be calculated as a function of device operation, rendering the thermal impedance model incompatible with the ETCS modification described in Chapter One. Second, the physical accuracy gained by using (5.16) did not translate to a significant improvement in the overall accuracy of the thermal impedance model. Therefore, the improvements offered by the use of (5.16) did not justify the complexity of its implementation, and the original approach used by Sharma and Ramanathan [Sha83] was retained.
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161 5.2.1 The Linear Source Thermal Impedance In the original model developed by Sharma and Ramanathan, the potential in the fielddependentvelocity portion of the channel was assumed to vary linearly along the length of the channel [Sha83]. This linearpotential assumption does not accurately represent the actual electric field in the channel. Due to the fielddependent velocity, the surface potential varies parabolically with position along the length of the channel, such that ^s(y) = Is 2 VJ V 2 (5.17) where V ls = V ds for the linear region of operation and V ls = V dss for the saturated region of operation. Therefore, using the relation P = I Â• E , the energy generation per unitarea can be expressed more accurately as gisCy'1 ') = 2 ' P ls (t j WL 2 (5.18) The temperature rise at any point (x, y, z) in the channel due to the linear source is calculated by substituting (5.13) and (5.18) into (5.12), and then integrating over the width and length of the channel. Assuming a step increase in power dissipation at t' = ( P ls (t) = P, s Â• U(t) ) and expressing the temperature rise as AT ls (t) = Z THls (t) Â• P ls , (5.19)
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162 yields the transient thermal impedance of the linear source V2x ,pcWL 2 77rat 74at V jAax n i y\j (IW^' + y eif ^> erf (^3} Ge>* Â• ,5 20) Equation (5.20) represents the temperature rise at any point in the device normalized to a unitstep increase in power dissipation in the linear source. To account for a finite substrate thickness, (5.14) can be used in place of (5.13) in equation (5.12). The effect of accounting for the parabolic variation in the surface potential is illustrated in Figure 5.3, where (5.20) is compared to a thermal impedance model derived using the uniformfield assumption of Sharma and Ramanathan [Sha83]. Since assuming a uniform electric field does not accurately model the increased power dissipation near the drain, the original model significantly underestimates the steadystate thermal resistance in that region. For circuit simulation, a single value is needed to represent the effective operating temperature of the device. Therefore, the thermal impedance model given by (5.20) should be evaluated at a single point. Appropriate values for coordinates can be determined by tuning the temperature rise predicted by (5. 1 ) to measured data in a region of steadystate heat flow. Based on the extracted temperature data shown later in the chapter, the optimum point for the model evaluation was found to be (x = 0, y =0.95L,z = 0).
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163 ! 4.5 4.0 U 3.5 x <Â£ 3.0 u c 25 'la *Â§ 2.0 H 1.5 .0 G Â— OE = E(y) Q Â— BE = Constant 0.0 0.5 1.0 1.5 Channel Length, L (J.m) 2.0 Figure 5.3 Comparison of thermal resistance calculated assuming a uniform electric field, E, to the thermal resistance calculated using (5.18), for W = 2 urn. In both cases, the thermal resistance model was evaluated at (x = 0, y = L, z = 0).
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164 5.2.2 The Saturated Source Thermal Impedance The heat source that represents the power dissipation in the velocitysaturated portion of the channel is modeled by a line source located at the surface of the drain/channel junction. The energy generation per unit width can therefore be expressed as gÂ«(t ) = PÂ„(t') W (5.21) The temperature rise at any point (x, y, z) in the channel due to the saturated source is calculated by substituting (5.13) and (5.21) into (5.12), and then integrating over the width of the channel. Assuming a step increase in power dissipation at t' = ( P ss (t) = P ss Â• U(t) ) and expressing the temperature rise as A T ss (t) = Z THss (t)P, (5.22) yields the transient thermal impedance of the saturated source Z THss( X 'y' Z '0 = J 4pcWjiat /W/2 + x erf Â— Â—v 74at + erf /2x 4at exp (.o^W^v V 4at exp teJ' dt (5.23) Equation (5.23) represents the temperature rise at any point in the device normalized to a unitstep increase in power dissipation in the saturated source. To account for a finite substrate thickness, (5.14) can be used in place of (5.13) in equation (5. 1 2). The thermal impedance model given by (5.23) should be evaluated at a single point to
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165 provide an effective temperature rise suitable for circuit simulation. The optimum point for the evaluation of (5.23) is the same as for the linear source and is given by ( X = 0, y = 0.95 L, z = 0). 5.2.3 Effects of the Device Interconnects on the Thermal Impedance For the derivation of the bulk MOSFET thermal impedance model, the surface of the substrate is assumed to be adiabatic. In actual devices, however, the drain, source and gate are in direct contact with interconnects that are used to electrically connect different devices on a chip. For the drain and source, the interconnects are typically fabricated using aluminum metallization, where the gate is usually contacted with polysilicon. The interconnects represent additional conductance paths which can enhance the heat transfer away from a device. Since the model neglects any such heat conduction, there is a question as to whether or not the heat loss via the interconnects significantly influences the thermal response of a device. Threedimensional (3D) finiteelement (FE) thermal simulations of a bulk MOSFET structure, using the ANSYS software package, were performed to examine the effects of the device interconnects on the thermal impedance. Two FE models were developed to separately investigate the effects of the drain/source interconnects and the gate interconnect; these models represented simplified device structures and were constructed using similar assumptions and boundary conditions to those detailed in Chapter Two. The FE simulations tend to over predict the heat conduction through the interconnects since the device, contacts and interconnects
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166 were considered to be in perfect thermal contact, so that any contact resistances at the material interfaces were neglected. While the FE models do not truly represent and actual device structure, they serve as an orderofmagnitude estimate for the effects of the interconnects on the thermal response. Figure 5.4a shows the FE model used for investigating the effects of the drain/source interconnect metallization on the thermal resistance. Steadystate thermal simulations were run with the interconnects present and with the interconnects removed. The results of the two groups of simulations were compared to determine the extent of the effect of the drain/source interconnects. The simulations were performed at various channeltocontact spacings (L d ) , for a fixed interconnect thickness (d met ) and a fixed oxide thickness (d ox ) between the interconnects and the substrate; the results are shown in Figure 5.4b. Overall, the effect of the drain/source interconnect metallization is to reduce the thermal resistance of a device; though, for the simulated devices, this effect is relatively minor. However, the data does illustrates how the drain/source interconnects become more effective thermal conductance paths as they are moved closer to the channel, or as their crosssectional area is increased. Therefore, the effects of the drain/source interconnects on the thermal resistance of highlyscaled MOSFET's could be more significant. The effects of the gate interconnect on the thermal resistance of bulk MOSFET's are examined by performing steadystate thermal simulations with the FE model shown in Figure 5.5a, both with and without the interconnect present. The gate material was assumed to be heavilydoped polysilicon such that the width of the
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167 (a) 0.0 0.2 0.4 0.6 0.8 L d (Jim) 1.0 1.2 1.4 (b) Figure 5.4 ANSYS simulations showing the effect of the drain/source interconnects on the thermal resistance, for d met = 0.7 im and d ox = 0.7 im: a) The finiteelement model simulated with ANSYS; b) the variation between the thermal resistance accounting for the drain/ source interconnects and the thermal resistance neglecting the drain/ source interconnects, plotted as a function of the edgetoedge distance between the channel and the contact openings.
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168 (a) 3 5 7 Channel Width, W (im) (b) Figure 5.5 ANSYS simulations showing the effect of the gate interconnect, assumed to be heavilydoped polysilicon, on the thermal resistance, for d g = 0.3 im, d gox = 10 nm and d ox = 0.15 im: a) The finiteelement model simulated with ANSYS; b) the variation between the thermal resistance accounting for the gate interconnect and the thermal resistance neglecting the gate interconnect, plotted as a function of the channel width.
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169 interconnect was equal to the length of the channel. The simulations were run at various channel widths, for both shortand longchannel devices with fixed interconnect (d ) and gateoxide (d ) thicknesses; the results are shown in Figure 5.5b. As with the drain/source interconnects, the effect of the gate interconnect is a reduction in the device thermal resistance. The trends in the data show that this effect decreases for devices with large channel widths; and, at a fixed channel width, the reduction in the thermal resistance is more significant for longer channel lengths. However, due to the relatively low thermal conductivity of the gate oxide and heavilydoped polysilicon, the extent of the effect is only moderate. Consequently, the use of silicided gate materials and ultrathin gate oxides, which effectively enhance the thermal conductance of the gate interconnect, could result in a more substantial reduction in the overall device thermal resistance. Transient thermal simulations of the FE models in Figure 5.4a and Figure 5.5a were performed to examine the effect of the device interconnects on the dynamic temperature response. Figure 5.6 shows the results of the simulations for a stepincrease in power dissipation. For the simulation with the drain/source interconnects, the thermal response does not deviate from that of a device without interconnects until the heat generated in the channel reaches the contacts. At this time, the additional heat capacity of the interconnect metallization effectively reduces the thermal response. The time it takes for the heat to reach the drain/source contacts can be approximated as the square of the distance L d divided by the thermal diffusivity of the substrate material. For the simulated device structure, the resulting time is approximately one nanosecond, which agrees with the FE simulations. The
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170 3.5 ee Â— b O O With Drain/Source Interconnects Q Â— Q Without Drain/Source Interconnects Time (sec) (a) 1010 4 10 2 1.2 ! u io X o o 1 0.5 S 1 0.2 H o.o 6 10 12 e Â— o ODD Q Â— OWith Gate Interconnect Q Â— Q Without Gate Interconnect Time (sec) (b) 0" 10" 10" Figure 5.6 ANS YS simulations showing the effects of the device interconnects on the transient thermal impedance: a) For the drain and source interconnects with W = 2 (im, L = 0.35 urn, d ox = 0.7 im, d met=Â°7 l Im ' w m = 5 7 ^m and L d = 1.2]im; b) for the gate interconnect with W = 4 im, L = 2 \im, d ox =0.15 im, d gox = 10 nm and d = 0.3 (im.
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171 gate interconnect affects the thermal response almost instantaneously since it is located directly above the channel. As with the drain/source interconnects, the gate interconnect represents an additional conductance path for heat to travel away from the channel, and its heat capacity reduces the thermal response of a device. However, since the thermal conductivity of heavilydoped polysilicon is relatively low, the effect of the gate interconnect on the dynamic temperature response is not substantial. Based on the results of the 3D FE simulations, neglecting the effects of the device interconnects in the model derivation should not result in substantial errors for larger MOSFET' s. However, the effects of the interconnects on the thermal impedance can become more severe for highlyscaled devices. In such a case, the thermal impedance model will tend to overpredict both the steadystate thermal resistance and the transient rise of the thermal impedance. 5.2.4 Effects of Isolation Structures on the Thermal Impedance As shown in Figure 5.1, a bulk MOSFET is typically surrounded by a region of silicondioxide which is used to electrically isolate it from neighboring devices. Such isolation is especially important for reducing latchup in CMOS circuits. The isolation technologies commonly used in bulk MOS fabrication are semirecessed LOCOS (local oxidation of silicon) and shallow trench (e.g. BOX isolation) [Wol90]. Since the isolation structures use Si0 2 , which has a low thermal conductivity, they will naturally impede the flow of heat away from a device. The bulk MOSFET thermal impedance represents the substrate as a homogeneous
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172 material, and therefore neglects the effects associated with oxide isolation. To understand the limitations associated with this assumption, the effects of isolation structures on the thermal response should be investigated. Threedimensional (3D) finiteelement (FE) thermal simulations, using ANSYS, were performed to examine the effects of isolation structures on the thermal impedance of bulk MOS transistors. A single FE model was developed to investigate the effects of both LOCOS and shallowtrench isolation. The full thickness (d fox ) of the isolation oxide was assumed to be recessed beneath the surface of the substrate. The model represented a simplified device structure and was constructed using similar assumptions and boundary conditions to those detailed in Chapter Two. The sidewalls of the isolation structures were assumed to be perpendicular to the top surface of the substrate, and were directly adjacent to the active device region. The implications of assuming vertical isolation walls are detailed in Chapter Two, where it is shown that the isolation structure model should over estimate the effects of the isolation. Therefore, while the finiteelement model does not truly represent the physical device layout, it provides an orderofmagnitude estimate for the effects of the isolation structures on the thermal impedance. Figure 5.7a shows the FE model used for investigating the effects of the isolation structures on the thermal resistance. Steadystate thermal simulations were run for various deviceisolation spacings (L dox ) ; this spacing corresponds to the distance between the channel and the edge of the isolation structure, along the length of the device. Simulations were also run for the same devices with the isolation structures removed; Figure 5.7b compares the results of the FE simulations. The
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173 (a) 20 u o c .2 15 Â© Â— OW = 2nm BaW = 4im AW = 8 im 0.8 1.0 1.2 1.4 L dox (urn) (b) 1.6 1.8 2.0 Figure 5.7 ANSYS simulations showing the effect of LOCOS or shallow trench isolation on the thermal resistance. The device specifications are L = 0.35 im and d fox = 0.4 im: a) The finiteelement model simulated with ANSYS; b) the variation between the thermal resistance accounting for the isolation and the thermal resistance assuming a homogeneous substrate, plotted as a function of the distance between the channel and the isolation (along the length of the device).
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174 oxide used in the isolation structures impedes the lateral flow of heat away from the device, resulting in an increased temperature rise over the device simulated with no isolation. The simulation data shows that this effect can be significant and increases for smallgeometry devices with small deviceisolation spacings. The increase in temperature rise can be reduced by decreasing the depth of the isolation structures or by moving the isolation away from the channel. Transient thermal simulations of the FE model shown in Figure 5.7a were performed to examine the effects of both LOCOS and shallowtrench isolation on the transient thermal impedance. ANSYS was used to simulate the device with and without the isolation structure present; the results are shown in Figure 5.8. The transient temperature response is affected in the same manner as the steadystate response, and as the heat travels laterally and reaches the edges of the isolation structure, the temperature rise accounting for the isolation begins to increase over the response without the isolation. Based on the results of the 3D FE simulations, neglecting the effects of the isolation structures used in bulk MOSFET technologies can be considered reasonable for larger devices. However, for highly scaled devices where the effective deviceisolation separation is small, the model will tend to considerably underpredict both the steadystate thermal resistance and the transient rise of the thermal impedance.
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175 E eee BÂ— B Â©With Isolation Â•Q Without Isolation 0"Â° Time (sec) 6 10 4 10" Figure 5.8 ANSYS simulations showing the effect of LOCOS or shallow trench isolation on the transient thermal impedance. The specifications for the device structure are W = 2 im, L = 0.35 im, d fox = 0.4 im, L dox = 12 Jim.
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176 5.3 Verification of the Bulk MOSFET Thermal Impedance Model To verify the ability of the thermal impedance model to predict the steadystate thermal resistance of bulk MOSFET's, the model was compared to measured temperature data. The temperature rise in the measured devices was predicted by evaluating the model equations (5.20) and (5.23) as t Â— > Â°Â° and then applying them to (5.1). The measured data were extracted using a gateresistance thermometry technique [Goo95]. Figure 5.9, Figure 5.10 and Figure 5.1 1 show the comparisons between the predicted and measured values for the temperature rise. The thermal impedance model accurately predicts the steadystate temperature rise, and hence the thermal resistance, for both shortand relatively longchannel MOSFET's; the average error between the model and the measurements was 1 1% and 3% for the onevolt and twovolt gate biases, respectively. The thermal impedance model was also compared to threedimensional (3D) transient finiteelement (FE) simulations performed using ANSYS. verification. Two FE models were developed to separately verify the linear and saturated source transient impedances. To simplify the FE simulations, the MOSFET structures were assumed to be symmetric about the yaxis (see Figure 5.2); therefore, only onehalf of a device was simulated. The device interconnects and device isolation were neglected and the substrate was assumed to be silicon with the bulk properties given in Table 5.1. The FE simulations were compared to the transient thermal impedance models given by (5.20) and (5.23), using the modification for finite substrate thickness; the results are shown in Figure 5.12 and Figure 5.13. The models for both the linear and saturated sources accurately replicate the transient and steadystate
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177 1 2 Power (mW) (a) U o B 3 Â— E H Power (mW) (b) Figure 5.9 Temperature rise, extracted using gate resistance thermometry, in Motorola bulk MOSFET's with W = 120 im and L = 0.65 im. The drain voltage was swept from 0.0 to 2.0 V: a) 1.0 V on the gate; b) 2.0 V on the gate.
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178 2 3 Power (mW) (a) 20 Power (mW) (b) 30 40 Figure 5.10 Temperature rise, extracted using gate resistance thermometry, in Motorola bulk MOSFET's with W = 120 (xm and L = 0.45 ^m. The drain voltage was swept from 0.0 to 2.0 V: a) 1.0 V on the gate; b) 2.0 V on the gate.
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179 U u e 3 k. u a. E (U H Power (mW) (a) 20 30 Power (mW) (b) 50 Figure 5.11 Temperature rise, extracted using gate resistance thermometry, in Motorola bulk MOSFET's with W = 120 [tm and L = 0.35 urn. The drain voltage was swept from 0.0 to 2.0 V: a) 1.0 V on the gate; b) 2.0 V on the gate.
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180 2.0 o o o r> o o n msrb OANSYS Model 1010" 3.5 0.06O 10 12 10 10 i Â— 000000 oonn> OANSYS Â— Model 1010" Time (sec) (b) 10" 10" Figure 5.12 The transient thermal impedance of the linear source simulated with ANSYS and calculated with the model: a) For W = 2 im, L = 0.65 urn; b) for W = 1 urn, L = 0.35 urn.
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181 4.5 Â£ 4.0 E p 3.5 ? 3.0 X t$ 2.5  2.0 r & 1 5 1 1.0 J 0.5 > H o.o Â©e 10 12 O O O O O O CXED OANSYS Â— Model v4 10 2 10 I I Â— I I 1 1 III I Â— J O O O O O O OOGO OANSYS Â— Model 0"Â° ioTime (sec) (b) 10 4 10" Figure 5.13 The transient thermal impedance of the saturated source simulated with ANSYS and calculated with the model: a) For W = 2 fim, L = 0.65 im; b) for W = 1 im, L = 0.35 urn.
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182 temperature response; for the device structures that were simulated, the error between the FE and analytical models is no greater than 13%. Since the parameters for the bulk MOSFET thermal impedance model are based solely on the device geometry, the model can be applied to predict the expected trends for selfheating in highlyscaled devices. Figure 5.14 shows the thermal resistance, of both the linear and saturated sources, plotted as a function of channel length. The model predicts that as bulk MOSFET's are scaled beyond quartermicron channel lengths, a substantial increase in the thermal resistance can be expected. Therefore, selfheating could become a significant problem in future generation devices and circuits. 5.4 Summary A thermal impedance model for bulk MOSFET's was derived. The model was shown to agree reasonably well with threedimensional finiteelement simulations and measurements of bulk devices. Since the model does not account for interconnect metallization and either LOCOS or trench isolation, the effects of neglecting such structures were investigated. The results suggest that the model can be expected to provide reasonable predictions for the thermal impedance of larger bulk devices. However, for highlyscaled devices, the effects of the drain, gate and source interconnects and isolation structures can be significant and the accuracy of the model will decline. Methods for modeling the effects of isolation structures are proposed in Chapter Eight.
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183 100 G Â— Â©Linear Source Q Â— Q Saturated Source B b=e= 3 2.0 Channel Length, L (im) Figure 5.14 Thermal resistance calculated using the model evaluated at steadystate, plotted as a function of channel length for W/L = 2.
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CHAPTER 6 A QUASITHREEDIMENSIONAL THERMAL IMPEDANCE MODEL FOR SILICONONINSULATOR METALOXIDESEMICONDUCTOR FIELDEFFECT TRANSISTORS 6.1 Introduction Metaloxidesemiconductor fieldeffecttransistors (MOSFET's) fabricated using silicononinsulator (SOI) substrates offer many advantages over MOSFET's fabricated using bulk wafer technologies. Device speed can be enhanced due to the reduction of the parasitic capacitances to the substrate [Tu94, Goo95]. The improved device isolation prevents latchup in complementary MOSFET (CMOS) circuits since the buried oxide layer eliminates the parasitic bipolar devices between transistors [Wol90]. Shortchannel effects can also be reduced due to the limited vertical depletion depth imposed by the finite silicon film thickness [Wol90]. Finally, the use of SOI substrates improves radiation hardness and can increase the device packing density [Wol90]. SOI MOSFET's are commonly fabricated using SIMOX (separation by implanted oxygen) SOI wafers. Figure 6.1 shows a diagram of a typical SOI MOSFET. SIMOX wafers are created by implanting oxygen ions into a silicon substrate. The implant is followed by a hightemperature anneal in an inert ambient to form silicon dioxide (Si0 2 ) [Wol90]. The oxygen is implanted far enough into the silicon such that the Si0 2 is buried beneath the wafer surface; typical values for the 184
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185 r Interconnects Y////Z&,
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186 thickness of the buried oxide layer range from 0.2 to 0.5 fim [Tu94, Goo95, Lee95]. Once the buried oxide layer is formed, the surface silicon layer is used for the fabrication of the MOSFET's, which can follow the standard process steps used for bulk devices. Typical values for the thickness of the silicon film range from 0.04 to 0.2 urn [Tu94, Goo95, Lee95]. Due to the low thermal conductivity of the buried oxide layer, MOSFET's fabricated on SOI wafers exhibit enhanced selfheating effects [Ber91, Che95, Jom95a]. Empirical extraction techniques using gate resistance thermometry or output conductance measurements have been developed to characterize the steadystate thermal resistance of SOI MOSFET's [Goo95, Lee95, Ten95]. The dynamic thermal impedance has also been extracted using output admittance or transient drain current measurements [Cav93, Cav95, Lee95]. The shortcomings of these methods are that they require complicated measurements or the fabrication of special test structures, and they do not provide predictive values for the thermal resistance or impedance. Physicsbased models have generally been limited to the steadystate thermal resistance [Ber91, Goo92, Che95, Jom95b]. A physical dynamic electrothermal model for SOI MOSFET's was developed by Bielefeld et al. [Bie95]. However, this model is solved using complex numerical techniques making it inefficient for circuit simulation. This chapter details the derivation of a compact physicsbased model for the dynamic thermal impedance of SOI MOSFET's. The thermal impedance model is an extension of a modified version of the steadystate thermal resistance model presented by Goodson and Flik [Goo92]. The work by Goodson and Flik provides an
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187 accurate model for the thermal resistance of SOI MOSFET's for which the width of the drain/source interconnect metallization approximately equals the width of the device, and the device interconnects play a significant role in heat evacuation. However, for many analog and some digital applications, the width of the device is greater than the metallization width, and the heat flow becomes dominated by the silicon film. While the model developed by Goodson and Flik allows separate input parameters for each width, it does not accurately model heat flow for the case where the device width is greater than the width of the metallization. The first part of this chapter reexamines the Goodson and Flik model and presents a modification to correct for the case where the device width is greater than the width of the drain/ source interconnects. The impact of the modification is examined through comparisons to the original model and measurements. The second part of the chapter then details the derivation of the dynamic thermal impedance model. The accuracy of the dynamic model is supported with threedimensional finiteelement simulations and measurements. 6.2 Derivation of the SOI MOSFET Thermal Resistance Model The thermal resistance model represents a solitary SOI MOSFET with three parallel conductance paths that carry heat away from the channel. These heatflow paths are illustrated in Figure 6.2 and are modeled by a system of coupled onedimensional differential equations. The derivation of the thermal resistance model is divided into separate regions that correspond to the different thermal conductance
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188
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189 paths. Different subscripts are used to denote the equations and variables that apply to the different regions; the subscript f is used as a generic identifier, and the subscripts c, g, d, m and ct apply to the channel, gate interconnect, drain/source regions of the silicon film, drain/source interconnects and the drain/source contact regions, respectively. Figure 6.3 shows the simplified device structure that defines the geometry for the model derivation. The definitions of the model parameters are listed in Table 6.1. The channel region is modeled as a heat source with uniform power dissipation and is assumed to be at a uniform temperature T c . In reality, the heat generation rate in the channel has a strong spatial dependence due to variations in the surface potential along the channel. However, the isothermal channel approximation was shown to be valid for predicting the average channel temperature, giving results typically within 10% error [Goo95]. The interface between the buried oxide and the silicon substrate is assumed to be at a uniform temperature T , and the device is assumed to cool solely through the substrate. As shown in Chapter Two, the thermal conductance to the overlying oxide layers is generally much smaller than the conductance to the substrate; therefore, heat loss through the overlying oxide layers can be neglected. The gate interconnect, the drain and source, and their metal interconnects are treated as onedimensional cooling fins that carry heat away from the channel. The differential equations that describe the temperature rise along the respective fins are given by
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190 source interconnect buried oxide *gate interconnect Figure 6.3 The simplified device geometry used to define the solution domain for the SOI MOSFET thermal resistance model. The model parameters are defined in Table 6.1.
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191 Table 6.1 SOI MOSFET thermal resistance model parameters Parameter
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192 ^I4^m ^AT d (x d ) = 0, (6.1) 9x d 5 2 AT m (x m ) m r^
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193 h t = p (6.7) a fo is the heat transfer coefficient from the fin to the substrate. The heat transfer coefficient is derived by solving the onedimensional, steadystate heat conduction equation in the underlying oxide layers. Values for the necessary material properties are listed in Table 6.2. The variable d fo corresponds to the total oxide thickness between a fin and the substrate, so that d do = d box' (6.8) d mo = d box + d fox + d LTO' (69) and d go = d box + d fox Â• (6.10) Assuming that the temperature along each fin is onedimensional, neglects the temperature gradients in the vertical and lateral directions within each fin. The validity of this assumption can be evaluated using the Biot number, which corresponds to the ratio of the internal and external thermal resistances for a given fin [Ozi93]. If the Biot number is much less than unity, then the fin can be approximated by a onedimensional thermal medium. The vertical Biot number for a fin is expressed as B vt = h f d f /k f . For B vf to equal 0. 1 , the thickness of the fin (d f ) would have to be approximately 5, 12 and 2 times greater than d fo for the drain/ source, drain/source interconnects and the gate interconnect, respectively.
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194 Table 6.2 Material properties Property
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195 Consequently, for typical SOI MOSFET geometries, the vertical temperature gradients in the fins can be neglected. The lateral Biot number for a fin is given by 2 B Lt = h f WjV(k f d t ) . For the drain/source interconnects, assuming they are routed in the first metal layer, B Lm approaches unity when W m = \3jd^; for practical metallization geometries, the lateral temperature gradient can be neglected. For a highlydoped polysilicon gate interconnect, the relatively low thermal conductivity can lead to more significant lateral temperature gradients. However, these gradients should be substantial only for channel lengths greater than 1 .2 fim. Due to the effects of the drain/source contacts and interconnects, the heat flow in the silicon film is more complex and the lateral Biot number is not valid for these regions. ANSYS simulations of the drain/source silicon film regions are used to evaluate the nature of the heat flow; the results are shown in Figure 6.4. The simulations show that for low thermal conductances to the substrate (i.e thicker buried oxides), the effect of the drain/source interconnects can lead to significant lateral temperature gradients in the silicon film. However, the model accurately predicts the average temperature distribution in the drain/source silicon film, showing that the onedimensional approximation is reasonable for these regions. The temperature rise of the silicon film at the edge of the channel (x d = L d ) and of the gate interconnect at x = are given by AT d (x d ) = AT (x e ) 1 + WÂ„d ggox dÂ„k k k W T g g o d l = AT C . (6.11) x g =
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196 90 70 U Bd d = 0.2 im d box = Â°5 ^ m o Â© ANSYS: Edge of Channel a b ANSYS: Middle of Channel Model 0.0 d d = 0.04 fim dbox = 0.2 Jim 0.1 0.2 Distance Along Drain/Source Region, x d (im) (a) 0.3 U o ANSYS: Edge of Channel a ANSYS: Middle of Channel Model d d = 0.04 nm d box = 02 ^ m 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Distance Along Drain/Source Region, x d (im) (b) Figure 6.4 Temperature along drain/source regions as calculated by ANSYS and predicted by the model for an SOI MOSFET with W = 12 u.m and W m = 2 im (center contact). The ANSYS data is evaluated at both the center and the edge of the channel, to show the extent of the lateral temperature gradient: a) For L d = 0.3 u.m; b) for L d = 1.2 fim.
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197 where k is the thermal conductivity of the gate oxide. The multiplier for the gate interconnect temperature accounts for the thermal resistance of the gate oxide by assuming rÂ£2* = o, (6.12) 8x AT I = AT C (6.13) g x =0 and AT I = AT (x ) . (6.14) e x = d s s x = Goodson and Flik assumed that the thermal resistance of the gate oxide was negligible since d is typically very small [Goo92]. However, (6.1 1) shows that the effect of the gate oxide thermal resistance can become more significant if k decreases or k increases; both conditions are probable in advanced SOI MOSFET's due to phonon boundary scattering in the gate oxide and the use of silicides for the gate interconnect material. The effect of the gate oxide can be removed by setting d = 0, in which case, the model reverts to the original model developed by Goodson and Flik [Goo92]. At the interface between the silicon film and the drain/source interconnect metallization (x d = x m = 0), the temperatures of the silicon and the metal are assumed to be equal and the heat flows are equated, giving the boundary conditions
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198 AT m ( x J n = AT d( x d) x m = x d = (6.15) k m W m d m Â• ^T m (x m ) 3xÂ„ k d Wd d x m = ^AT d (x d )n 3xj = 0. (6.16) Equation (6.16) is the boundary condition derived by Goodson and Flik, and is valid when W = W m [Goo92]. However, since the thermal analysis for the drain/source silicon film region only extends to the edge of the interconnect contact, when W > W m (6.16) neglects heat flow from the portions of the silicon film under the contact. Figure 6.5 illustrates the portions of the silicon film that are neglected by (6.16). The heat flow from these portions of the silicon film through the buried oxide is proportional to WW m ; thus, the error introduced by neglecting this heat flow increases as W becomes greater than W m . To account for heat flow from the portions of the drain/source silicon film under the contact, (6.16) is modified. Due to the high thermal conductivity of the metal contact, the silicon film under the contact is assumed to be at a uniform temperature. For large devices where the contact area is divided into multiple contact windows, significant lateral temperature gradients can develop. ANSYS simulations are used to examine the heat flow in the silicon region under the contact; the results are shown in Figure 6.6. Even for conditions that cause considerable lateral heat flow, the model gives an accurate account of the average temperature in the silicon film under the contact. Therefore, the uniform temperature assumption can be considered appropriate. To account for the neglected conduction, an additional heatflow term is added to (6.16), so that the modified boundary condition becomes
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199 Figure 6.5 The simplified SOI MOSFET structure for the case where W > W m . The crosshatched regions represent the portions of the drain/source silicon film where heat flow is neglected by the Goodson and Flik model [Goo92].
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200 175 U o U Â— 3
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201 k m W m d m
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202 and arg2 = exp(m d L d )(m d k d d d Wh d (WW m )L ct m m k m d m W m ). (6.22) For the case where W < W m , the expression for the thermal resistance is equivalent to the Goodson and Flik model [Goo92] and argl = exp(m d L d )(m d k d d d W + m m k m d m W m ) (6.23) arg2 = exp(m d L d )(m d k d d d Wm m k m d m W m ). (6.24) The differential equations that describe the temperature rise in each cooling fin neglect the temperature dependences of the material thermal conductivities. However, the measured data plotted in Figure 6.7 show that the temperature dependence of the SOI MOSFET thermal resistance is relatively weak. For the devices used in the measurements, the extracted thermal resistances vary by less than 3% over a 90 Â°C temperature range. Therefore, it is assumed that the temperature dependences of the thermal conductivities can be neglected. 6.3 Verification of the SOI MOSFET Thermal Resistance Model The accuracy of the SOI MOSFET thermal resistance model derived by Goodson and Flik has been verified [Goo92, Goo95]. The model was shown to agree with thermal resistance measurements of devices with W
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203 880 C 860 U o X & 840 o o 8 820 "c3 H 800 780 i !
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204 MOSFET's with W = 120 fxm and W m = 2 pm were measured using a fourpoint, gate resistance thermometry technique [Goo95]. Figure 6.8 compares both models to the measured thermal resistance values. By neglecting the heat flow out of the contact regions, the model developed by Goodson and Flik [Goo92] tends to overestimate the thermal resistance, in this case by as much as 40%. With modification to account for the heat flow out of the drain/source contact regions implemented, the model provides a much more accurate estimation of the thermal resistance. For the given devices, the error is reduced to no more than three percent. 6.4 Derivation of the SOI MOSFET Thermal Impedance Model The thermal impedance model for SOI MOSFET's is derived by extending the steadystate thermal resistance model into the time domain. The timedependent form of the differential coolingfin equation can be expressed as 9 2 AT f 2 i 3AT f 3x f ^[m f (t)]AT f= ^t(6.25) where a t = k f /(p f c pf ) is the thermal diffusivity of the fin material. Values for the additional material properties needed to calculate the thermal diffusivities are listed in Table 6.3. In the time domain, (6.25) does not have a simple closedform solution. However, a simple solution to (6.25) can be found in the frequency domain using the Laplace transform.
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205 1300 1200 U 1100 c 1 1000 f15 C 900 800 700 ' 1 ' 1
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206 Table 6.3 Material properties Property
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207 In the frequency domain, the differential equations (6.1), (6.2) and (6.3) become 9 3"0 d (x d , s) [ 2 s 1 1 [m d (s)] 2 + f e d (x d ,s) = (6.26) 3x d a d. a 2 e m (x m ,s) f 2 s 1 Â—^f [m m (s)] 2 + l9 m (x m ,s) = (6.27) 3x m I u m J a^e s (x e , s) 2 s g 2 g [m g (s)] 2 + A 9 g (x g ,s) = (6.28) dx' [ a g) where f (x f , s) = Â£ [AT f (x f , t)] is the Laplace transform of the timedomain temperature rise and the initial condition in each fin is specified as AT f (x f , 0) = [Ozi93]. Examining (6.26), (6.27) and (6.28), shows that the differential cooling fin equation can be expressed in the same form for either the steadystate or the frequency domain. Therefore, the frequencydomain differential coolingfin equations have closedform general solutions given as f (x f , s) = c,exp(Y f x f )+c 2 exp(Y f x f ) (6.29) where Y f = [m f (s)] 2 + A (6.30) CXf
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208 and Cj and c 2 are arbitrary constants that depend on the boundary conditions. The use of the Laplace transform requires that the temperature rise remains a linear function of the power dissipation over the desired region of operation. Since the thermal resistance only depends weakly on device bias and temperature, this assumption is valid for typical device operation. As mentioned in the first part of this chapter, the characteristic thermal length, l/m f , of a cooling fin accounts for heat conduction through the underlying oxide layers. During a thermal transient, the characteristic thermal length will vary, l/m f = l/m f (s) , due to the time dependence of the heat transfer in the underlying oxide. Using the steadystate heat transfer coefficient to calculate the characteristic thermal length would imply that the heat flux in the buried oxide instantaneously adjusts to a steadystate value. Therefore, the heat transfer coefficient for the fin, h f (s) , becomes a function of frequency and should be derived from a dynamic analysis of the heat flux in the underlying oxide. Assuming the heat flow in the oxide is predominantly onedimensional, the temperature rise in the underlying oxide is described by a 2 AT (n,t) i 9AT (n,t) where AT (n, t) = T (n, t) T , a o is the thermal diffusivity of silicon dioxide and n is the direction of heat flow. Taking the Laplace transform of (6.31) results in a 2 e (n, s) s Â£5Â— e o (n,s) = 0. (6.32)
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209 where the initial temperature rise in the oxide is assumed to be AT (n, 0) = 0. The fin and the underlying oxide are assumed to be in perfect thermal contact, so that at the interface between the fin and the oxide e (s) = e f (s) (6.33) The interface between the buried oxide and the substrate is still assumed to be at the temperature T , so at that interface e n (s) = o. (6.34) The heat flux at the interface between the fin and the oxide can be derived from the solution to (6.32) for the given boundary conditions, and is given by 30 (n, s) I ' /Â— d fo 1 exp 2 / Â— d V a/cl fo 6 f (s) . (6.35) Therefore, the dynamic heat transfer coefficient can be expressed as h f (s) = k o JIcc
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210 and e m (x d ,s) =0. (6.38) The boundary condition at the edge of the channel becomes 0d( x d> s ) , =r goxl 6(x s) =6 c (s) (6.39) where r l+exp(2y gox d gox )  k g y g W g d g [lexp(2 Yg0X d g0X )] gÂ° xl 2exp(Ygox d gox ) 2k goxYgox WLexp(Ygox d gox ) and 'V^gox (6.40) (6.41) Equation (6.40) is derived by solving (6.32) in the gate oxide for the boundary conditions implied by (6.13) and (6.14). The boundary conditions that define the temperature and heat flow at the interface between the drain/source regions and the interconnect metallization become e m( x m> s ) =9d( x d> s ) n (642) and
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21 = k m W m d m 3x m k d Wd d + h d (s)[WWJL ct 9 d (x d ,s) ^d( x d^)l x d = 0. (6.43) x d = The Laplace transform of the power conservation equation that couples the conductance paths is p(s) = 2k d Wd d [ae d (x d , s> 3x, k g w g d g X.. Â— L,. Â•36 g (x g> s)i 3xÂ„ Â• r gox2 x g = o (6.44) + h d (s)WLe c (s) where 2exp(y d ) gox2 [exp(2y d )+l]^eoxTeox^ ^ k 2 Y 2 d e W [^(^YaoX^Ox)1 ] g g g (6.45) and p(s) = Â£[p(t)] is the Laplace transform of the instantaneous power dissipation in the channel. Equation (6.44) can be solved in the form AT C = Z TH (s)p(s), (6.46) resulting in the following expression for the dynamic thermal impedance ^th' s ) Â— 2(arg larg2)k d y d d d W r1 argl + arg2 + k g Tg d g W g r gox2 + h d (s)W Â• L (6.47) where
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212 argl = exp[L d Y d ]{k d Y d d d W + h d (s)[WW m ]L ct + k m y m d m W m } (6.48) and arg2 = exp[L d y d ]{k d y d d d Wh d (s)[WW m ]L ct k m y m d m W m }. (6.49) 6.5 Verification of the SOI MOSFET Thermal Impedance Model To verify the thermal impedance model, threedimensional (3D) finiteelement (FE) simulations of an SOI MOSFET were performed using ANSYS. The FE model represented a simplified device structure and was constructed using similar assumptions and boundary conditions to those detailed in Chapter Two. The model was further simplified by neglecting the gate interconnect. Figure 6.9a shows the FE model used to represent the SOI MOSFET structure in ANSYS. The thermal impedance was extracted from the FE simulations by averaging the temperature rise over the channel region. The ANSYS results are compared to (6.47) with the term corresponding to conduction in the gate interconnect set to zero. The comparisons are illustrated in Figure 6.9b, Figure 6.10, and Figure 6.1 1. The SOI MOSFET thermal impedance model displays reasonable trends with the scaling of the silicon film thickness, the buried oxide thickness, and both channel width and length. The model does a good job of reproducing both the transient and steadystate temperature responses produced by the 3D FE simulations. For the device structures that were simulated, the error between the model and ANSYS did not exceed 14%. As is evident from the comparisons in Figure 6.10, the discrepancy between the model and the FE simulations is greatest during the latter half of the transient. This trend can be
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213 (a) o 12 10 o e a a Cm a OANSYS Â— Model S 8 6 2 10 13 eQ o oo 5 10" Figure 6.9 The transient thermal impedance simulated with ANSYS and calculated with the SOI MOSFET thermal impedance model: a) The finiteelement model simulated with ANSYS; b) comparison of the thermal impedance simulated with ANSYS and the model for W = 8 Jim, L = 0.35 im, L d = 0.6 ^m, d d = 0.15 im, d box = 0.4 urn, W m = 2 ixm and d m = 0.9 im.
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214 15 U o S 10 X 0) o c cd T3
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215 o O
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216 attributed to the lack of modeling of the contact structure itself. The model effectively assumes that the thermal resistance and capacitance of the contact structure is negligible. For devices with a large contact area, this assumption is valid. However, for devices with a relatively small contact area, the effectiveness of the drain/source interconnects as heat conductance paths is diminished. The temperature in such devices will rise quicker and to a greater magnitude than predicted by the model. The extent of the discrepancy can be reduced by tuning the width (and/or thickness) of the drain/source interconnects to reduce their effect on the thermal impedance. Equation (6.47), in the complete form, was also compared to measured thermal impedance data extracted by Lee and Fox using transient drain current measurements [Lee95]. Figure 6.12 compares the measured and simulated data for a transient thermal impedance of an SOI MOSFET fabricated at Texas Instruments. Again, the model accurately predicts both the steadystate and transient temperature response. Part of the discrepancy at the earlier times is due to the finite rise time of the pulse used in the measurements. The model, as calculated for Figure 6.12, represents the temperature response to an ideal step in power dissipation, and will show a faster rise than the measurements. 6.6 Summary Due to the low thermal conductivity of the silicon dioxide used for the buried oxide isolation, the thermal impedance of SOI MOSFET's is typically larger
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15 U o 10 x U e a a u aM 5 15 xi 217 i r 1 Â— i Â— i i i i I Measurement Model _i i i ' I i t i i i I 10 9 icr love I0~ 10" Time (sec) Figure 6.12 Measured and simulated data for the transient thermal impedance of a Texas Instruments SOI MOSFET with W = 2.4 (im, L = 1.8 urn, d d = 0.17 im and d box = 0.33 u.m.
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218 than that of their bulk counterparts. Therefore, selfheating effects can be enhanced and it is important to have a physical model that can predict the dynamic temperature rise. This chapter presented a physical thermal impedance model for SOI MOSFET's. The model was shown to agree reasonably well with both threedimensional finiteelement simulations and measurements.
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CHAPTER 7 THE THERMAL IMPEDANCE PREPROCESSOR: TIPP 7.1 Introduction The most common way to incorporate dynamic thermal effects into circuit simulators, using a thermal impedance to model the effective temperature rise in a transistor, is described in Chapter One. The analogy between electrical and thermal behavior can be used to represent the thermal impedance with a thermal equivalent circuit consisting of discrete resistances and capacitances. Consequently, thermal equivalent circuits provide a suitable means for efficient DC, AC and transient electrothermal circuit simulation. For steadystate heat conduction, there is a simple correspondence between the thermal impedance and the thermal equivalent circuit: the sum of the resistance components in the thermal equivalent circuit is equal to the thermal spreading resistance. However, for a full dynamic thermal response, the correlation between the thermal impedance data and the component values of the thermal equivalent circuit is more complex. Thus, there is a need for a consistent and efficient approach for generating the component values from dynamic thermal impedance data. This chapter presents a computer program that implements a systematic approach for calculating the component values of the thermal equivalent circuit. The 219
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220 general operation of the program is discussed briefly. The numerical algorithms used to generate the thermal equivalent component values from thermal impedance data are examined in some detail. Examples of calculated thermal equivalent circuits are presented and a method for interfacing the program with electrothermal circuit simulators (ETCS's) is discussed. 7.2 A Description of TIPP The Thermal Impedance PreProcessor (TIPP) was developed to facilitate the use of ETCS's for modeling selfheating effects in semiconductor circuits. TIPP is a standalone software package for the specific purpose of providing an ETCS with access to thermal impedance models and the component values for their thermal equivalent circuits. The evolution of TIPP as a precircuitsimulation processor serves three purposes. First, the complexities of modifying an ETCS program to incorporate a thermal impedance model are avoided. The modifications would be specific to each circuit simulator and each thermal impedance model; therefore, the modifications would have to be repeated for each implementation. Second, the numerical burden of calculating the component values for the thermal equivalent circuit is removed from the circuit simulator. Third, TIPP was designed to provide an open framework for the generation of physicsbased thermal impedance models and their thermal equivalent circuits; and therefore, gives a modifiable platform which can be accessed by any ETCS. TIPP is written in a modular format using the C programming language. The program structure allows for the easy addition of new
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221 thermal impedance models or new numerical algorithms. At the present time, TIPP contains the physicsbased models that are derived in the preceding chapters. While physicsbased models offer the predictive capabilities that are useful in a development environment, they can not always provide the necessary accuracy required by a design environment. In such cases, the precision of optimized empirical data is essential. The numerical methods that TIPP uses to generate the thermal equivalent circuit are independent of the data source; therefore, TIPP can use either measured thermal impedance data or the predictive physical models to generate the component values for the thermal equivalent circuit. The output from TIPP is in the form of a netlist which contains the components for any necessary thermal equivalent circuit(s). The generated thermal equivalent netlist can then be incorporated into an existing circuit file in preparation for an electrothermal simulation. The TIPP program structure is simple and was designed to provide results without drastically increasing the complexity of circuit simulation. TIPP is invoked from the command line using the parameters in Table 7.1. Table 7.1 TIPP commandline parameters Name Description filename sp sa Name of file that contains input for TIPP Option flag to instruct TIPP to use SPICE format for output file (filename. sp) Option flag to instruct TIPP to use SABER format for output file(s) (filename. sin)
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222 The basic operation of TIPP is outlined by the flowchart shown in Figure 7.1. The input for TIPP is contained in a text file that is composed of a set of instruction parameters, which are defined in Table 7.2. Table 7.2 TIPP input parameters Name
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223 Parse TIPP input file Approximate time constants Generate thermal response from model Calculate resistance components Calculate capacitance components Figure 7.1 A flowchart illustrating the general operation of the TIPP software package
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224 haddix a 0EV soimos DATA phys NP 5 W 8 L 0.35 LD 0. 6 LCT . 6 LM 10 WM 2 WG 1 DD 0.1 DM 0. 9 DG 0.3 DBOX 0.4 DOX 1 Figure 7.2 Example of a TIPP input file for an SOI MOSFET. The first three lines contain the TIPPspecific parameters for the simulation. The other parameters are used to describe the geometry of the transistor.
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225 7.3 Generation of Thermal Equivalent Circuits In Chapter One, the representation of a thermal impedance using circuit elements was discussed, and for this work, a Foster network was chosen to model the normalized temperature response. The components for the thermal equivalent circuit are generated by numerically fitting the multiplepole network response to thermal impedance data; which TIPP assumes is in the form of a normalized (units of Â°C/W) transient step response or a normalized frequency response. Therefore, the network response of the thermal equivalent circuit must be derived in both the frequency and time domain. The voltage generated across the thermal equivalent circuit can be expressed as V(s) = I(s) Â• Z TH (s) , (7.1) where V(s) represents the effective temperature rise of the device and I(s) represents the power dissipation. The normalized temperature response for an impulse in the power, where the Laplace transform of the impulse function is Â£[5(t)] = 1 , is simply equivalent to the impedance of the thermal equivalent circuit. Thus, for an n stage Foster network, the thermal impedance can be expressed as rj , , r thl r th2 r thn ,~ ~, Z TH (s) = Â— + Â— + Â•Â•Â•+Â— , (7.2) 1H 1+s/cO] + s/co 2 + s/co n where r th is the j th thermal resistance component, ^r th j = R TH is tne thermal spreading resistance and CO: is the jth pole. Equation (7.1) yields the temperature
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226 response to a unit step function, U(t) , when I(s) = 1 /s . Therefore, the timedomain thermal step response can be derived by multiplying (7.2) by 1/s and taking the inverse Laplace transform. The resulting expression is Z TH (t) r thl P U" + r th2 expl Â— \x 2 + +r thn expg (7.3) where x, is the i th time constant and co ; = 1/T: . j J j j 7.3.1 Approximation of the Thermal Equivalent Poles/Time Constants The first step in generating the thermal equivalent circuit is to calculate the pole or time constant associated with each stage of the thermal equivalent circuit. The initial approach used to calculate each pole/time constant was nonlinear optimization. The efficiency of the optimization algorithm was strongly dependent on the number of poles/time constants and the accuracy of the initial guess for the poles/time constants. However, the accuracy of the thermal equivalent circuit fit was found to be relatively insensitive to the exact location of the poles/time constants. Figure 7.3 shows an example of the variation in the fit accuracy that can occur when the locations of the poles/time constants are shifted. The variation in the fit accuracy was typically less than five percent for a ten percent change in any pole/time constant, and was never greater than ten percent. The results are typical for each thermal impedance model over most practical device geometries. Consequently, the insensitivity of the fit accuracy to the pole/time constant location can be exploited to develop a heuristic approximation for calculating the location.
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227 ^ o Z D o c C3 lÂ— > < G Â— 0+10% Variation in Each x ; B Â— Q10% Variation in Each X; Number of Poles Figure 7.3 Example of the variation in the accuracy of a thermal equivalent circuit due to changes in the location each time constant. The bulk bipolar model is used to generate the thermal impedance data. The time constants of the thermal equivalent circuit are independently varied by ten percent in either direction. The difference norm between the thermal impedance data (TID) and the thermal equivalent circuit (TEC), /s /(TID 1 TEC,) 2 + (TID 2 TEC 2 ) 2 ++(TID m TEC m ) 2 , is calculated for m discrete data points. The variation in the difference norm is averaged over each time constant.
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228 The algorithm for approximating the poles/time constants employs a binary search procedure that "scans" the thermal impedance magnitude for specific points. Figure 7.4 shows a graphical illustration of the algorithm when used to approximate five poles of a thermal equivalent circuit from a frequencydomain thermal impedance. For each stage of the thermal equivalent circuit, a single point is found which corresponds to a certain percentage, < Pj < 1 , of the impedance maximum, max. The corresponding frequencies/times at which these points occur are used to approximate the poles/time constants. The value used for each percentage, p j? was determined from the results of the original optimization algorithm performed on the bulk bipolar thermal impedance model. The model was evaluated for a wide range of device geometries and the final value for each percentage was taken as the average over this range. Though the values for the percentages were calculated for a specific model, they tend to be independent of the thermal impedance data source and provide accurate fits in most cases. The aforementioned approach for determining the location of the poles/ time constants for a thermal equivalent circuit is simple and more efficient than numerical optimization. However, this technique is not completely robust, and could produce erroneous results if there is sufficient noise is present in the thermal impedance data. Notwithstanding, the open program structure of TIPP would allow the use of possibly more robust techniques such as moment matching [Pil94].
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229 max 000000000 Pj*max p 2 *max U o O O E 15 p 3 *max H p 4 *max p 5 *max Thermal Impedance Data MultiplePole Fit CO] co 2 co 3 co 4 Frequency (Hz) Â€^) Figure 7.4 Illustration of the algorithm that TIPP uses to approximate the poles/ time constants for a thermal equivalent circuit. In this example, a fivepole thermal equivalent circuit is fit to a frequencydomain thermal impedance. The magnitude of the thermal impedance is scanned for specific points that correspond to certain percentages, pj, of the impedance maximum, max. The frequencies at which these points occur are used to approximate the poles, 0);, of the thermal equivalent circuit.
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230 7.3.2 Calculation of the Thermal Equivalent Components After the necessary poles/time constants are predicted, the resistance and capacitance components of the thermal equivalent circuit can be calculated. Equations (7.2) and (7.3) show that the response of the thermal equivalent circuit is linearly proportional to the resistance components. Thus, the resistance components can be efficiently derived by minimizing the discrete leastsquares error between the thermal impedance data and the response of the Foster network. A constraint is placed upon the thermal resistance components such that for an n stage thermal equivalent circuit n = ssresp(r,+r 2 ++r (n _ 1) ) , (7.4) where ssresp is the steadystate value of the thermal impedance data; therefore, the system of unknowns is reduced from n to (n1) independent variables. The leastsquares approach along with (7.4) yields the following system of linear equations A, A. A A 12 22 L l(n1) L 2(n1) A (n1)1 A (n1)2 Â•Â•Â• A (nl)(nl)
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231 V= I exp^)exp(^ ' l f _t > exp Â— exp n k /J (7.6) and r,= I "^HKv, Â• < respj ssresp 1 exp tjYl (7.7) when using (7.3) to fit a normalized thermal step response, resp, with m discrete data points. If resp corresponds to a normalized thermal frequency response, equation (7.2) is used to fit the data so that V = I i = 1 1 +Sj/a)j 1 + Sj/(JL) n l+s/co k L+s/to n (7.8) and r,= I i = 1 1 + Sj/Cflj + s/co n respj ssresp Â• l+s/co n (7.9) The n resistance components can be calculated by solving (7.5) and (7.4). Since the resulting coefficient matrix is never larger than 4x4, Gaussian elimination and backsubstitution are used to solve the system of linear equations. After the resistance components are determined, the capacitance components can be calculated using the following equation
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232 c thj = V r thj = l/ (Â°>j r thj)(7 10) Examples of complete thermal equivalent circuit fits are shown in Figure 7.5. The thermal equivalent circuits show good agreement with the thermal impedance data generated from both measurement and a physicsbased model. The plots also illustrate how the distributed nature of the thermal impedance is more accurately represented by thermal equivalent circuits using multiple poles. 7.4 The Interface Between TIPP and Circuit Simulators The last operation of the TIPP program is to output the calculated resistance and capacitance components of a thermal equivalent circuit. Since TIPP is intended to function as a companion to any given ETCS, the format of the output should be consistent with the syntax of that simulator. Therefore, the interface that TIPP uses to communicate with an ETCS should be flexible and convenient. The role of a preprocessor was chosen so that TIPP's own program structure would be independent of ETCS program syntax. While this approach is not as immediate as directly coupling TIPP to an ETCS, it avoids the unwieldy modifications, to both circuit simulator and TIPP, that would be required to implement a direct interface. Since it is simple to modify or extend the TIPP program alone, its output can be constructed in a format that is compatible with any ETCS. As shown in Table 7.1, TIPP's output can be formatted for either a SPICEtype or the SABER [Sab95] circuit simulator. This output is written to a text file, or group of text files, that can easily be incorporated into an existing circuit file. If a specific
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150 U o X if o T3 1) E 100 E 50 c3 1) C H 10 12 " ' 233 Â— i Â— i i n i i f "O" e Â— e Â— eOThermal Impedance Model 1PoleTh. Eq. Circuit Â— 3Pole Th. Eq. Circuit Time (sec) (a) 0' 10" 10 L 150 1 1 Â— i i i i i i Â— I 1 1 Â— i Â— rrrrr* u o X u o a
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234 output format is not selected, TIPP writes a simple list of the components for each thermal equivalent circuit. For SPICEtype circuit simulators, TIPP writes a single output file (filename. sp) that contains a subcircuit netlist for each thermal equivalent circuit. For the MEBJT/MEHBT thermal impedance model, the output file will also contain a subcircuit for the complete device. The MEBJT/MEHBT subcircuit consists of the necessary transistor cards and elements to model each finger and each thermalcoupling network. For the SABER circuit simulator, TIPP writes one output file (filename. sin) for each generated thermal equivalent circuit. Each file contains the corresponding netlist in the proper SABER template format. If the MEBJT/MEHBT thermal impedance model is used to generate the thermal equivalent circuits, a separate output file is created for the MEBJT/MEHBT electrothermal model. As with the SPICEformatted output, the MEBJT/MEHBT template contains the netlists for the necessary thermalcoupling networks. The formats used to generate the SPICE and SABER output files are shown in Figure 7.6 and Figure 7.7, respectively. If a circuit simulator does not use either of the mentioned formats, the TIPP program can be easily extended to provide the required output format. 7.5 Summary In order to investigate thermal effects in circuits and devices, circuit simulators have been modified to account for dynamic temperature variations. The temperature response of a device can be modeled by its thermal impedance, which
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235 * Subcircuit for Thermal Equivalent Circuit .subckt 1 (np+ 1) Z rthl 1 2 cthl 1 2 rth(np) np (np + 1) cth(np) np (np+ 1) .ends Z * Subcircuit for MEBJT/MEHBT .subckt 12 3 4 MEBJT * Thermal Coupling Networks xsl os (os + 1) ZS ecl2(os+l) (os + 2) ncp ncn 1 eclnf (os + nf 1 ) (os + nf) ncp ncn vsl (os + nf) fpl (os + nf + 1) vsl 1 xc21 (os + nf + 1) (os + nf + 2) ZC1 xcnfl (os + 2nfl) ZC(nfl) .ends MEBJT Figure 7.6 Template for TIPP output in SPICE format, where os is an arbitrary offset for the node numbering.
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236 # Template for Thermal Equivalent Circuit template Z 1 (np+ 1) { r.rthl 1 2 = value c.cthl 1 2 = value r.rth(np) np (np + 1 ) = value c.cth(np) np (np+l)= value } # Template for MEBJT template MEBJT 12 3 4 { # Thermal Coupling Networks ZS.zsl os (os + 1) vcvs.tcl2 ncp ncn (os+1) (os + 2)=k=l vcvs.tclnf ncp ncn (os + nf1) (os + nf)=k v.vsl (os + nf) 0=0 cccs.pl i(v.vsl) (os + nf + 1) = k = 1 ZCl.zc21 (os + nf +1) (os + nf + 2) ZC(nfl).zcnfl (os + 2nfl) } Figure 7.7 Template for TIPP output in SABER format, where os is an arbitrary offset for the node numbering.
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237 can be derived from physical models or extracted from measurements. Multiplepole thermal equivalent circuits provide an efficient method for incorporating thermal impedance data into a circuit simulation. The TIPP computer program was developed as a general framework for thermal impedance modeling. TIPP generates thermal equivalent circuits using its internal physicsbased models or imported measured data. The flexibility of the TIPP program structure allows new thermal impedance models to be added easily and simple interfacing with electrothermal circuit simulators.
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CHAPTER 8 CONCLUSIONS AND RECOMMENDATIONS FOR FUTURE WORK 8.1 Conclusions The primary goal of this dissertation was to develop physical models that could predict the thermal impedance of semiconductor devices and also remain efficient enough to be used for circuit simulation. Four thermal impedance models were presented for different device structures, all of which satisfy the abovementioned conditions. Each model is derived from the physical heat conduction equation, and is therefore capable of accurately predicting the thermal impedance based solely on material properties and device geometry. In addition, the models are in the form of compact analytical expressions which produce results quickly, therefore offering a more efficient alternative to costly numerical thermal simulations. The development of thermal impedance models for BJT's, on both bulk and SOI substrates, was detailed in Chapters Two and Four. The bulk BJT model, originally developed by Joy and Schlig [Joy70], was extended to account for finite substrate thickness and devices with multiple emitters. The DIBJT model was derived to depict the complete transient temperature response and was then simplified to produce an additional model for the steadystate thermal resistance. Both models were augmented to account for the thermal resistance and heat capacity 238
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239 of the emitter interconnect metallization. In addition, threedimensional finiteelement simulations were used to show that the effects of advanced dielectric isolation on the thermal impedance of bulk BJT's can be significant for highlyscaled transistors. In Chapter Three, a circuit model for thermal coupling between devices in a common substrate was derived. The circuit representations were developed to facilitate the implementation of the multipleemitter BJT thermal impedance model in circuit simulation; however, they are also applicable to the general case of thermal coupling between arbitrary devices. The thermal coupling model was then used to develop an extraction methodology for an efficient, lumped electrothermal model for multipleemitter BJT/HBT's. Thermal impedance models for MOSFET's, on both bulk and SOI substrates, were described in Chapters Five and Six. The bulk MOSFET model improved on the work by Sharma and Ramanathan [Sha83] by accounting for crosswidth temperature gradients and the linear variation of the electric field along the length of the channel. Threedimensional finiteelement simulations were used to investigate the effects of device interconnects and isolation on the thermal impedance of bulk devices. The SOI MOSFET model was based on a modified version of the steadystate thermal resistance model developed by Goodson and Flik [Goo92]. The modified steadystate model was extended for timedependent heat conduction to produce the dynamic thermal impedance model. In Chapter Seven, the Thermal Impedance PreProcessor (TIPP) was introduced. The TIPP software program was developed to provide efficient and
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240 systematic algorithms for generating thermal impedance models and the thermal equivalent circuits necessary for electrothermal circuit simulations. Finally, a number of the accomplishments that were the result of this research, have been documented in various journal and conference publications. These papers are cited, as follows, in the reference list at the end of this dissertation [Bro93, Bro97, Fox93a, Zwe95a, Zwe95b, Zwe96]. 8.2 Recommendations for Future Work The thermal impedance models presented in this dissertation can provide accurate predictions when used within the limits of their derivations. However, the robustness of the models, over a wider range of device structure types and sizes, can be enhanced further. Two areas are presented for future research that could improve the accuracy of the models. In addition, a third research topic concerning thermal coupling in SOI MOSFET circuits is suggested. 8.2.1 The Temperature Dependence of the Thermal Conductivity The heat conduction equation used to derive the thermal impedance models in this dissertation assumes that the thermal conductivity is constant, and therefore independent of temperature. For small to moderate temperature excursions, this assumption is valid; however, for a large temperature rise (50100 Â°C) above the reference ambient, the thermal conductivity can vary by as much as 31% [Gao89]. Such large temperature excursions in transistors are common in highpower
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241 applications and therefore, the accuracy of the thermal impedance models could be improved by accounting for the temperature dependence of the thermal conductivity. The variation of the thermal conductivity with temperature makes the heat conduction equation nonlinear, such that V.k(T)VT + g = pc p , (8.1) where the temperature dependence of the specific heat is assumed to be relatively weak compared to that of the thermal conductivity. The Kirchoff transformation [Joy75] linearizes (8.1) by using the following variable transformation T(t) = T + l f k(T)dT, (8.2) 1 o where k is the thermal conductivity at the reference ambient temperature, T . The relation between the linear and nonlinear temperature variables can be examined by multiplying both sides of (8.2) by k , taking the gradient and then the divergence, resulting in k V 2 8 = V.k(T)VT = pc p jg. (8.3) Consequently, if the temperature dependence of the thermal conductivity is known and can be expressed as an integrable equation, (8.2) can be used to correct the temperature calculated with the linear heat conduction equation.
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242 The correction to the estimated temperature, accounting for the temperature dependence of the thermal conductivity, can be implemented in an electrothermal circuit simulator by adjusting the voltage generated at the temperature node. Preliminary attempts at such a modification have shown that the approach is viable. However, the implementation must de handled carefully to ensure consistency between the thermal and electrical solutions, and to reduce possible convergence problems. It is suggested that further research be conducted to ascertain the optimum approach for incorporating the Kirchoff transformation into an electrothermal circuit simulator. 8.2.2 Models for Thermal Effects Due to Advanced Isolation The thermal impedance models for bulk BJT's and MOSFET's described in Chapters Two and Five, neglect the effects of the oxide isolation structures (e.g. LOCOS or trench) used to electrically isolate devices in a common substrate. Due to their low thermal conductivity, these isolation structures can significantly increase the thermal impedance of highlyscaled devices. Consequently, there can be substantial errors between the results predicted by the models and actual observed thermal impedances. Therefore, the bulk models should be modified to improve their accuracy for highlyscaled devices that are fabricated with advanced isolation structures. By implementing the Green's function technique that is detailed in Chapter Four, both the bulk BJT and bulk MOSFET thermal impedance models can be modified to account for isolation structures. Adapting this analysis to the bulk
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243 models would require that the physical device be divided into two domains, which can be thought of as intrinsic and extrinsic thermal regions. The intrinsic thermal domain can be approximated by a rectangular volume with boundaries defined at the surface of the substrate, at the depth of the isolation structure and at the interfaces between the intrinsic electrical device and the "sidewalls" of the isolation structure. The extrinsic thermal domain would represent the exterior portions of the substrate that surround the isolation structure. The threedimensional heat conduction equation would be solved within the intrinsic thermal domain. The thermal boundary conditions would be derived from the nature of the thermal conduction in the extrinsic thermal domain. The difficulty in this implementation, lies in the derivation of the boundary conditions. It is suggested that the ANSYS finiteelement solver be employed to extensively simulate isolated device structures. From these simulations, reasonable assumptions can be formulated to simplify the heat conduction analysis in the exterior thermal domain for different isolation structures. Once the thermal analysis is simplified, boundary conditions for the intrinsic thermal domain can be deduced. 8.2.3 A Model for Thermal Coupling in SOI MOSFET Circuits For MOSFET's fabricated in a common substrate using a bulk technology, thermal coupling between devices is due primarily to heat transport through the substrate. In such cases, the thermal impedances that describe the thermal interactions between devices can be modeled using the analysis similar to that in Chapter Two for MEBJT's. Due to the insulating properties of the buried and field
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244 oxides, MOSFET's fabricated on an SOI substrate might be considered thermally isolated from one another. However, recent work by Tenbroek et al. [Ten96] showed that there can be thermal coupling between MOSFET's on a common SOI substrate. Since SOI devices are effectively isolated within the substrate, the dominant mechanism of thermal coupling between MOSFET's is the heat conduction through the device interconnects. The effects of thermal coupling in an SOI MOSFET current mirror are illustrated in Figure 8.1; the circuit shown in the inset is modeled after the current mirrors measured by Tenbroek et al. [Ten96] and was simulated in SOISPICE [Fos95]. The reference device and device Ml are assumed to be located in close proximity of one another such that there is significant thermal coupling. Device M2 is assumed to be located a relatively large distance away from the other devices, and is therefore thermally isolated. The drain voltage of M2 is fixed while the drain voltage of Ml is allowed to vary. The drain current of device M2 should be equivalent to, or mirror, the drain current of the reference device and should be independent of V D1 . However, as the simulation shows, the drain current of M2 does depend on the drain voltage V D] . This phenomenon can be explained by the thermal coupling between Ml and the reference device. As the power in Ml increases, the temperature in the reference device will increase. Since the drain current of the reference device is fixed, the gate voltage will have to increase to counter the effects of the reduced carrier mobility caused by the increase in temperature. Therefore, the gate voltage of M2 will also increase, resulting in an increase in drain current.
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245 840 830 820 Q
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246 A preliminary model for thermalcoupling impedance between SOI MOSFET's, which was used for the simulation in Figure 8.1, has been developed. However, the model is not complete. Twoand threedimensional ANSYS simulations, used in conjunction with measurements of the test structures shown by Tenbroek et al. [Ten96], are suggested to further the development and validate the accuracy of the thermalcoupling impedance model. Once the model is complete, it can be used with a physicsbased circuit simulator, such as SOISPICE [Fos95], to investigate the effect of thermal coupling in a wide range of SOI circuits.
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254 [Nis91] H. Nishizawa, S. Azuma, T. Yoshitake, K. Yamada, T. Ikeda, H. Masuda and A. Anzai, "A Fully Si0 2 Isolated SelfAligned SOIBipolar Transistor for VLSIs," in Proceedings IEEE Bipolar Circuits and Technology Meeting, Minneapolis, MN, pp. 5358, 1991. [Ona95] Takahiro Onai, Eiji Ohue, Yohji Idei, Masamichi Tanabe, Hiromi Shimamoto, Katsuyoshi Washio and Tohru Nakamura, "SelfAligned Complementary Bipolar Technology for LowPower Dissipation and UltraHighSpeed LSI's," IEEE Transactions on Electron Devices, vol. 42, no. 3, pp. 413417, March 1995. [Ozi93] M. Necati Ozisik, Heat Conduction . Second Edition, John Wiley & Sons, Inc., New York, 1993. [Pil94] Lawrence Pillage and Ronald A. Rohrer, "The Essence of AWE," IEEE Circuits & Systems Magazine, pp. 1219, September 1994. [Pru94] A. Pruijmboom, C. E. Timmering and J. J. E. M. Hageraats, "18 ps ECLGate Delay in Laterally Scaled 30 GHz Bipolar Transistors," in Technical Digest IEEE International Electron Devices Meeting, San Francisco, CA, pp. 825828, 1994. [Sab95] SaberGuide and SaberScope Manual, Version 4.0, Analogy, Inc., Beaverton, OR, December 1995. [Sch84] A. Schutz, S. Selberherr and H. W. Potzl, "Temperature Distribution and Power Dissipation in MOSFETs," SolidState Electronics, vol. 27, no. 4, pp. 394395, April 1994. [Sei93] Ulrich Seiler, Eric Koenig, Peter Narozny and Heinrich Dambkes, "Thermally Triggered Collapse of Collector Current in Power Heterojunction Bipolar Transistors," in Proceedings IEEE Bipolar Circuits and Technology Meeting, Minneapolis, MN, pp. 257260, 1993. [Sha83] D. K. Sharma and K. V. Ramanathan, "Modeling Thermal Effects on MOS IV Characteristics," IEEE Electron Device Letters, vol. EDL4, no. 10, pp. 362364, October 1983.
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256 [Wor97] Glenn Workman, Jerry Fossum, Srinath Krishnan and Mario Pelella, "Physical Modeling of Temperature Dependences of SOI CMOS Devices and Circuits Including SelfHeating," submitted to IEEE Transactions on Electron Devices. [Yam93] Tad Yamaguchi, Sudarsan Uppili, Galen Kawamoto, June Lee and Shaun Simpkins, "Process and Device Optimization of A 30GHz fT Submicrometer Double PolySi Bipolar Technology," in Proceedings IEEE Bipolar Circuits and Technology Meeting, Minneapolis, MN, pp. 136139, 1993. [Zwe95a] D. T. Zweidinger, J. S. Brodsky and R. M. Fox, "A Physical Thermal Resistance Model for Vertical BJTs on SOI," in Proceedings IEEE International SOI Conference, Tucson, AZ, pp. 8485, October 1995. [Zwe95b] D. T. Zweidinger, R. M. Fox, J. S. Brodsky, T. Jung and S. G. Lee, "Extraction of Thermal Parameters for Bipolar Circuit Simulation," in Proceedings IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, MN, pp. 7881, October 1995. [Zwe96] David T. Zweidinger, Robert M. Fox, Jonathan S. Brodsky, Taewon Jung and SangGug Lee, "Thermal Impedance Extraction for Bipolar Transistors," IEEE Transactions on Electron Devices, vol. 43, no. 2, pp. 342346, February 1996. [Zwe97] David T. Zweidinger, Modeling of Transistor SelfHeating for Circuit Simulation , Ph. D. Dissertation, University of Florida, August 1997.
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BIOGRAPHICAL SKETCH Jonathan Brodsky was born in Philadelphia, Pennsylvania, on August 3, 1969. In 1991, he received the Bachelor of Science degree in electrical engineering from Lafayette College, Easton, Pennsylvania. He received the Master of Science degree from the University of Florida, Gainesville, in 1993, and in the same year began working towards the Doctor of Philosophy degree in electrical engineering. During the summer of 1995, he worked at the Motorola Advanced Products Research and Development Laboratory, Austin, Texas, where he helped characterize selfheating in SOI MOSFET's. Upon graduation he will join Texas Instruments, Inc. in Dallas, Texas, as a member of the Mixed Signal Products group working in the area of ESD protection. He is a member of The Institute of Electrical and Electronics Engineers. 257
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I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Robert M. Fox, Chairman Associate Professor of Electrical and Computer Engineering I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Mark E. Law Professor of Electrical and Computer Engineering I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. William R. Eisenstadt Associate Professor of Electrical and Computer Engineering I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. i*A/W^ Jcyyl G. Harris Assistant Professor of Electrical and Computer Engineering
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I certify that I have read this study and that in my opinion it conforms to acceptable standards of scholarly presentation and is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. ChenChi Hsu Professor of Aerospace Engineering, Mechanics and Engineering Science This dissertation was submitted to the Graduate Faculty of the College of Engineering and to the Graduate School and was accepted as partial fulfillment of the requirements for the degree of Doctor of Philosophy. August 1997 a Winfred M. Phillips Dean, College of Engineering Karen A. Holbrook Dean, Graduate School

